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Design Verification Engineer resume in Sunnyvale, CA - April 2024
Lushan Liu
408-***-**** ad42vq@r.postjobfree.com
SKILLS Assembly, Verilog, SystemC, SystemVerilog, UVM, Cadence JasperGold, IMC coverage, C/C++, Java, Perl/Python, C Shell scripts, MakeFile
Cadence Xcelium, Virtuoso, AMS, SPICE, Spectre, Verdi, SimVision, Synopsys FineSim, QuestaSim, Symphony AMS...
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