Lushan Liu

408-***-**** ad42vq@r.postjobfree.com

SKILLS Assembly, Verilog, SystemC, SystemVerilog, UVM, Cadence JasperGold, IMC coverage, C/C++, Java, Perl/Python, C Shell scripts, MakeFile

Cadence Xcelium, Virtuoso, AMS, SPICE, Spectre, Verdi, SimVision, Synopsys FineSim, QuestaSim, Symphony AMS Tool;

EXPERIENCES Senior Staff Analog Verification Engineer – Marvell Technology, Santa Clara, CA, June, 2021~ Present

● DSP High Speed Data Transfer Product: Wrote more than 50 testcases in UVM environment: Verified connectivity between digital and analog modules by register read/write, programming functionalities; Check the above in both transmit and receive side; DAC Calibration, Pseudo Random Generation data path; Wrote Python scripts to process standard cellname and module instances; Wrote presentation slides with simulation scenarios and results;

● PMIC DC/DC Converter: AMS verification for top level, including VerilogAMS stimulus; Maintaining Testbench schematics, configuration files and simulation maestro states; wrote RNM

(Real Number Model), VerilogAMS, verilogA models for about 60 analog modules (such as oscillator, resistor divider, DAC, ADC, RC compensation, LDOs, Bandgap Bias generator, level shifters); Develop chip top level verification plan; interaction between analog and digital components and tests partitioning; help provide SystemVerilog models to interact with digital;

● Top level test plan implementation: Wrote 20 UVM AMS testcases to verify powerup, buck ramp up/ramp down; various faults generation and clearing mechanisms; TEST buses (ATB/DTB assignments); OTP functionalities; using Virtuoso VIVA and Simvision to check results waveform in voltage and current; measure leakage currents for digital core;

● Helping team members with various Cadence tool and simulation issues and repository control

(SOS, svn, github) issues; familiar with the connect rule/module, IE card GUI or custom connect rule from global to submodules; familiar with setting up probe.tcl file or selections from tool save option; debug simulation functionality and speed issues; Staff Design Verification Engineer –Renesas Electronics America (former Intersil), Milpitas, CA, Dec 2013~June, 2021

● Participated in nine chips taped out:

Mixed Signal PMIC design verification in many teams at many locations, mainly in Milpitas, CA

(4 chips), also in Austin, TX (2 chips), North Carolina(2 Chips), UK (1 chip). The ICs range from digital multiphase control loop for servers; analog top multi-phase buck converters for handheld devices; Custom Integrated Charger PMIC with USB interface; Digital Controlled Panel PMIC; Optical Driver PMIC for medical use: The details are as follows:

● Multi-phase Buck Power Management ICs: Setup digital simulation environment, including testbench, stimulus; Developed functional tests in SystemVerilog; Developed bus functional model for I2C, PMBUS, SPI/SPMI transactions; wrote tests to verify digital components, including I2C/SPI, buck ramping, OTP download/programming, fault handling; Implemented SystemVerilog assertion based verification, gate level simulation; scan chain simulation; maintain regression and coverage; Running formal tool JasperGold with predefined functional checks such as dead code, FSM and arithmetic overflow checks; Running IMC for coverage analysis and merge coverage;

● PMBus based PMICs: Created and maintained PMBus testbench in custom PMBus driver and Cadence ViP; Verified PMbus various Commands and protocols including: Send Byte, Write Byte/Word, Read Byte/Word; Block write/read and Query process call; Packet Error Checking(PEC) calculation; Verified functionality of each commands;

● Optical Driver PMICs: Create and maintain both SystemVerilog and UVM testbenches; wrote testcases covering register map, safety and BIST; digital submodule verification such as state machine using UVM;

● Charger Power Management ICs: Design and setup the whole chip AMS simulation environment and the regression and coverage tool/scripts; developed functional tests at the digital and AMS environments using Virtuoso; Maintain analog models for AMS simulation/regression; running simulations for schematics vs models verification for various analog blocks;

● Digital multiphase control loop project; created testcases in C and SystemVerilog for ARM Cortex M0 to AHB Lite and I2C/SMBus/PMBus interfaces; verified firmware functionalities, including ROM integrity check with CRC; interrupt driven tasks; store/restore configurations with OTP

● PMIC Analog Component Verification: Verified Analog components by running Schematic vs. Model simulation, such Startup block functionality: VBG output base on TRIM values; VDDOK comparator; PVIN divider; Short circuit detection (power bus drop below certain level); Main LDO output based on the Trim value and VDD Margin; Temp Fault check by raising and lowering temp and state machine change accordingly;

Senior Design Verification Engineer, Marvell Semiconductor, Santa Clara, CA, Oct., 2007 ~ Nov, 2013

● ARM Compliant Processor Quad-core CortexA9/CortexA8/CortexR/ARM11MP/ARM1176 processor; Single-core dual-issue V7/V6/V5 processor, including ARM9;

● Architecture verification and Direct Test Generation for ARM microprocessor designs: Responsible for developing verification test plan, creating testbench; Verified sub-modules: Load Store Unit, Branch Prediction Unit, Neon/VFP Coprocessor. Developing testcases in Assembly and C, running regressions and debugging test failures and analyzing coverage with Questa;

● AXI/ACE Bus Protocol Verification: Verified Bus Interface and Cache Coherency by using Bus Functional Model (SystemVerilog and UVM); Without changing test environment, we insert AXI bus access sequence with SystemVerilog function calls and result checking with assertions;

● Responsible for Gate-Level Simulation for single and multi-core ARM-based processors: Integrating the testbench with the synthesized Gate Level; Integrated ARM AVS test suites to our environment. Catch issues in RTL, C reference model and ARM provided Verification Suite (AVS) tests, testbench/ISS model. Applied for ARM architecture license; Design Verification Engineer (Internship), Agere Systems now LSI, Allentown, PA, May, 2005~ Aug., 2005

● Network Attached Storage (NAS) Controller Chip: participated in the verification of TCP/IP protocol processing unit with NCSim-Specman environment; developed a hardware/software platform with VaST prototype to model the ARM, AHB, APB based SoC. NAS Chip was taped out for V1/V2;

Research Assistant, VLSI Research Lab, State University of New York, Aug., 2000~Sep., 2007

● Memory/Register File Design, Modeling and Testing (PhD Dissertation)

● Memory Circuit Design and CAD Tool Development: Power-aware memory system design for deep submicron SoCs; investigating transistor level techniques for low power CMOS SRAM designs; modeled memory access speed, power, area and process variations of cache memory circuitry in C programming language;

● SRAM Testing: Worked on defect analysis and fault modeling, investigated the failure mechanism in multi-port SRAMs;

Teaching Assistant, Department of Computer Science and Engineering, State University of New York, Aug, 2000~May, 2006

Selected Courses: Java C/C++ Programming Languages, Machine Learning; Advanced VLSI Digital Systems, ARM Microprocessors; Computer Networks, Analog Circuits, Analog Devices; EDUCATION ● Advanced SystemVerilog, UVM Testbench, and Formal Verification, Analog Circuits, University of California Santa Cruz (UCSC), Silicon Valley Extension, 2016~2022

● Ph.D. Computer Engineering,

State University of New York at Buffalo, Aug., 2003~Sep, 2007

● M.S. Computer Engineering,

State University of New York at Buffalo, Aug., 2000~Sep., 2003

● B.S. Computer Engineering,

Beijing Polytechnic University, Beijing, Sep., 1996~July, 2000

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