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Design State University

Fort Collins, CO
... SKILLS Cadence Virtuoso (DRC, LVS, QRC) FPGA Design (Xilinx ISE, Altera) C Python Perl Numpy, Scipy, PyML Cadence Encounter VHDL Verilog Assembly language System Verilog, UVM PROJECTS IN CADENCE, RTL CODING(VERILOG,VHDL) Synchronous Counter Designed ... - Jun 22

Quality Assurance Software Engineer

Diamond Bar, CA
... SQL, Linux, Software Development Life Cycle, Python, Functional Programming, JavaScript, GoLang, R, MIPS Assembly Language, Verilog HDL ● Eclipse and Microsoft Visual Studio as integrated development environment MATHEMATICAL SKILL SET ● Mathematical ... - Jun 22

Technical Support Sec School

India, Chennai, Tamil Nadu
... EDUCATION: COURSE NAME OF INSTITUTION YEAR Percentage% BE/ECE Adhi College OfEngg&tech 2010 -2014 68.2 HSC St Joseph Hr Sec School 2009– 2010 65.33 SSLC St Joseph Hr Sec School 2006– 2008 70 TECHNICAL SKILLS: Verilog HDL Networking DCA Typewriting ... - Jun 22

c, verilog HDL, assembly language for microcontrollrs

India, Pune, Maharashtra
... Programming Languages : C, VHDL, Basic Embedded C, ALP, Verilog HDL, Basic JAVA . Tools : Matlab,Keil, Xilinx ISE,Multism, Eclipse . WORKSHOPS &PRESENTATIONS Participated in Workshop on “ADVANCED ROBOTICS” at IIT Madras, 2013. Participated in ... - Jun 21

Verilog

India, Hyderabad, Telangana
... Key Skills: Having knowledge in HDL Language like “Verilog”. Good basic knowledge HVL language like “System Verilog”. Expertise in IUS, Encounter RTL Compiler SOC encounter, Cadence Virtuoso. Good knowledge in Xilinx. Good knowledge in “FPGA”. Good ... - Jun 20

Engineer High School

India, Bukkapuram, Andhra Pradesh
... Key Skills: Having knowledge in HDL Language like “Verilog”. Good basic knowledge HVL language like “System Verilog”. Expertise in IUS, Encounter RTL Compiler SOC encounter, Cadence Virtuoso. Good knowledge in Xilinx. Good knowledge in “FPGA”. Good ... - Jun 20

Computer Science Data

Thousand Oaks, CA
... { Translated some design specifications from English to Chinese { Wrote Verilog HDL testbenches on existing designs { Redesigned errorous modules Honors & Awards May, 2010– July, 2010 Selected Student of Chong Chi College as a summer school student ... - Jun 19

Engineer Electrical Design For Test

Gilbert, AZ
... •Extensive experience and strong knowledge of defining test strategy of a device, DFT Scan including SOC DFT Scan implementation, fault models, ATPG pattern generation, .TDF, test development, JTAG, RTL Verilog coding, scan insertion, synthesis, STA ... - Jun 19

Design Engineer

India, Delhi
... •Advance Workshop in Layout Design using Cadence – Virtuoso from ENTUPLE Technologies at IPEC TECHNICAL COMPETENCIES Languages Known - •Hardware Design:Verilog •Tools Used Design: Cadence-Virtuoso (VSEL, LayoutXL), Silvaco (Gateway, Expert), Symica. ... - Jun 19

Electrical Engineering Professional Experience

Union City, NJ
... - Windows (XP/ Vista/ 7/ 8/ 10), Mac OS, Linux - L-edit, Octave, Microsoft Office (Word, Excel and Outlook) - Python, Verilog, SQL, VHDL, System Verilog, C/C++ - Raspberry Pi, Arduino, Xilinx FPGA PROFESSIONAL EXPERIENCE Stevens Institute of ... - Jun 18
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