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FPGA / ASIC Design Engineer

Fullerton, CA
Stephen Cole **** ********** ***, *********, ** *2835 Email: aczhiq@r.postjobfree.com Relevant Qualifications: ASIC / FPGA Design Engineer with over 15 years’ experience of design, implementation, simulation and co-verification of Verilog and VHDL ... - Mar 25

Engineer Electrical

Los Angeles, CA
... Experience in using the C++ Standard Template Library (STL) and Verilog HDL. Experience working on Printed Circuit Board designing using PADS and Net list verification of PCB'S. Implementation of hardware circuit using P-spice/OrCAD. Experience in ... - Mar 25

Electrical Engineering State University

San Jose, CA
... Proficient in system level design and modeling with Verilog-A, MATLAB, C++, and VHDL programming language. Skilled in Electrical and Electronic software’s such as Cadence Virtuoso, Quartus-II, Multicim, Proteus Professional, Altium Designer, ADS, ... - Mar 24

Software Developer and Research Assistant

Ames, IA
... net, JSP, Javascript, JQuery, AngularJS, Objective-C, HTML, CSS, CCNA, Microcontrollers, Matlab, NodeJS, MULE ESB,ASP.net, Verilog, Connect IQ SDK, Monkey C, SpecC,Neo4J,Unity, XNA, MonoGame, d3.js,leaflet.js, Hadoop, HBase, Geospatial Technology, ... - Mar 24

Test Cases Project

India, Bengaluru, Karnataka
... Assembly level languages : VHDL, Verilog Tools : Xilinx, Cadence, Orcad Capture, Matlab, LabVIEW, Unity 3D, Selenium. PCB Designing : Orcad Capture, Orcad Editor (Cadence Allegro [16.3]) EDUCATIONAL QUALIFICATION Secured 77.4 % in MTech (VLSI Design ... - Mar 24

Physical Design Engineer Intern

Tempe, AZ
... Responsible for writing synthesizable RTL code in Verilog for complete standard cell library. Software Engineering Analyst – Accenture Services Pvt, Ltd. (Client: Bank of America) Aug’12 – Jul’14 Developed test suits and scripts in C for designing ... - Mar 24

Electrical Engineer Technical Support

Milford Mill, MD
... Computer Literacy Microsoft Office, Microsoft Visual C++, AutoCAD, Cisco Packet Tracer, MATLAB, Verilog, Xilinx Multi Suite - Mar 24

Electrical Engineering Engineer

Seattle, WA
... Electrical Engineering, GPA: 3.5/4.0 Jun 2013 – Jun 2015 Relevant Courses: Digital Logic with Verilog design, Circuit Theory, Energy Systems, Control System Analysis, Power System Analysis Passed Fundamentals of Engineering Exam (EIT) March/16/2017 - Mar 23

Electrical Engineer

Fremont, CA
... Veda IIT - Hyderabad, India ASIC Verification Trainee, July’2013 – July’2014 • Worked on the verification of an in house ASIC using VMM and System Verilog • Designed global tests for testing the overall functionality of the ASIC • Developed a ... - Mar 23

ASIC, SOC, FPGA, RTL, Verilog, C/C++, Verification, validation

Portland, OR
... PROFESSIONAL SUMMARY Proficient with C/C++, Verilog and System Verilog. Experience with design and verification of ASICs and SoCs. Sound knowledge of caches, different memories and its Validation techniques. Worked on Nexys4 DDR Artix-7 FPGA, using ... - Mar 23
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