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Design Engineer Engineering

Chicago, IL
... TECHNICAL SKILLS: • Operating Systems: Windows, Unix, Linux, IOS • Programming Languages: C, C++, VHDL, Verilog, RTL, TCL/Tk, Python, Assembly language of 8051, 8085, Ladder Language (PLC) • Application Software and Tools: MS Office Suite, MATLAB, ... - Mar 20

Mixed Signal-Rf/Analog/Asic Engineer

San Jose, CA
... Technical Proficiency Skills: ASIC/CMOS/RTL Design, Synthesis, Pipelining, Validation, FPGA Prototyping, Static Timing Analysis. Platforms: Windows 7, Windows 8 and MAC OS. Programming Languages: Verilog HDL, Verilog, C/C++. Software Tools: Synopsys ... - Mar 20

Service Management

India, Gujarat
... Good experience of Handling assembly line and PQC,OQC,IQC,RTL testing of mobile parts LCD,TSP,Camera,sensor,receiver,rear cover & travel adaptor charger, cable Successful management of team to obtain all results within specified target. Closure of ... - Mar 19

Engineering Computer

Gainesville, FL
... Aug 2016 – Jan 2017 Designed a RTL/Hardware wrapper around the LBM PE in Verilog for fast Data Streaming through PCI-e and timing Closure. Implemented an OpenCL framework for scaling the LBM Application across two Stratix V FPGA’s. Designed and ... - Mar 18

Engineer Design

San Jose, CA
... PROFESSIONAL SKILLS System verilog RTL programming in wide variety of projects Working knowledge of Xilinx and Altera FPGA design methodologies Working knowledge of PCIe/eMMC/SATA/SCSI and DDR2/GDDR LPDDR3/4 protocols Working knowledge of low power ... - Mar 16

Engineer Electrical

San Jose, CA
... Using Verdi to bring up waveforms during rtl module debugging. Writing script (c-shell, Perl) for compiling test before running, automate generating testbench module for test reusable and checking output of log file result to determine which tests ... - Mar 15

Electrical and electronic engineer

Harvey, IL
... ASIC Design and Performance analysis of Arithmetic Logic Unit (IBM 130nm technology) Jan 2016-April 2016 Developed an ALU ASIC layout and schematic from RTL level information. Designed a custom cell library utilizing ISE (Verilog), Design Vision ... - Mar 14

Engineer Project

Beaverton, OR
... Triage and debugging at block level Experienced in test plan development, test implementation, verification environment development, RTL simulations and verification Sign-off Hands on experience in VHDL, Verilog, System Verilog, Running Regressions, ... - Mar 14

Electrical Engineer Power Plant

Fremont, CA
GOVIND VUPPU #***, **** ****** ****** ***** : aczaer@r.postjobfree.com Fremont, CA-94536 Mobile: +1(669)-***-**** I AM CURRENTLY SEEKING AN OPPORTUNITY IN FIELD OF ASIC DESIGN OR VERIFCATION SKILLS: Technical skills: RTL-design, ASIC verification, ... - Mar 14

Engineer Project

India, Madhya Pradesh
... LTD.(January 2014 to June 2014) Designation:- Engineer BTS: Installation and Integration of ZTE Indoor 8800 BTS and 8909 Outdoor BTS for RTL and Tata Tele Services Ltd. Installation and Commissioning of Nokia Siemens Ultra, Flexi Indoor and outdoor ... - Mar 13
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