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Design State University

Fort Collins, CO
... SKILLS Cadence Virtuoso (DRC, LVS, QRC) FPGA Design (Xilinx ISE, Altera) C Python Perl Numpy, Scipy, PyML Cadence Encounter VHDL Verilog Assembly language System Verilog, UVM PROJECTS IN CADENCE, RTL CODING(VERILOG,VHDL) Synchronous Counter Designed ... - Jun 22

Business Developer, Channel Manager, Customer Support Manager, Sales

The Netherlands, Amsterdam-Zuidoost, NH
... market from scratch in the Benelux region by reaching out for prospect and successfully introduced and referenced our business to strategic accounts in various industries such as RTL, AWTC Europe, Philips TPVision, Test Aankoop, Proximus, Ericson. ... - Jun 21

Verilog

India, Hyderabad, Telangana
... Expertise in IUS, Encounter RTL Compiler SOC encounter, Cadence Virtuoso. Good knowledge in Xilinx. Good knowledge in “FPGA”. Good knowledge in “ASIC Design flow”. Educational Qualifications: Degree Institute Specialization Year % M-TECH Aurora’s ... - Jun 20

Engineer High School

India, Bukkapuram, Andhra Pradesh
... Expertise in IUS, Encounter RTL Compiler SOC encounter, Cadence Virtuoso. Good knowledge in Xilinx. Good knowledge in “FPGA”. Good knowledge in “ASIC Design flow”. Educational Qualifications: Degree Institute Specialization Year % M-TECH Aurora’s ... - Jun 20

Engineer Electrical Design For Test

Gilbert, AZ
... •Extensive experience and strong knowledge of defining test strategy of a device, DFT Scan including SOC DFT Scan implementation, fault models, ATPG pattern generation, .TDF, test development, JTAG, RTL Verilog coding, scan insertion, synthesis, STA ... - Jun 19

Electrical Engineering Design

Cincinnati, OH
... Linear Array Sorter Oct 2015 - Dec 2015 Designed a layout from RTL for a 4-bit serial I/O with linear time complexity. Demonstrated a bit-sliced design using CMOS library to form complex gates. The chip was sent to fabrication. Tools used: hSpice, ... - Jun 18

Technical Product Specialist

San Diego, CA
... India (GPA 8.77/10) RELEVENT COURSE WORK VLSI System Design, VLSI Circuit Design, VLSI ASICs Design, RTL Design, CMOS Logic Design, Digital Logic Design, Computer Architecture, Signal and Power Integrity, Digital Signal Processing, Modem Design. ... - Jun 16

Design Electrical Engineer

Arlington, TX
... Experienced in CMOS VLSI design, Verilog RTL coding, Simulation, Synthesis, Map and Place & Route, Layout (LVS). Experienced in ASIC front end/back end design, Physical Design flow, SOC Level Verification in System Verilog and C. Hands on experience ... - Jun 15

Design Engineer

Salem, NH
... Statistical modelling, optimization techniques Low-power designs Re-engineering Project management Technical skills Cadence: RTL Compiler, SOC Encounter Place & Route, Virtuoso, Spectre, OrCAD Synopsys: DC Compiler, PrimeTime STA, TetraMAX, HSPICE ... - Jun 15

Frontend UI Developer

Alpharetta, GA
... Team size 10 Customer Name McAfee – Infrastructure Team Project description The existing non-RTL websites had to be redesigned for RTL [Right-to-Left] display for 2 locales Tools & Technologies Adobe Photoshop, Dreamweaver, ASP, HTML, CSS, ... - Jun 14
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