Rtl Resumes

Sign in
Search for: Jobs   Resumes


Get new resumes like this by email Resumes 1 - 10 of 1631

FPGA,ASIC

India, Chennai, Tamil Nadu
V.P.Sampath acwumd@r.postjobfree.com Cell: +*19840163772 Summary: FPGA and ASIC RTL design for Communication Systems Expertise in designing of IPs for speed, area and power optimizations Simulation, Design Synthesis, Implementation, PAR, Timing ... - Sep 30

C++,Embedded System Design, Hardware Design, Python, C

San Francisco, CA
... • Experience in developing BFMs / Checkers / monitors / Scoreboards • Experience of 2 years in doing Research, developing RTL code in Verilog and verification using SystemVerilog • Designed a Video Motion Estimator chip using Verilog and ... - Sep 28

System Administrator Design

San Francisco, CA
... • Experience in developing BFMs / Checkers / monitors / Scoreboards • Experience of 2 years in doing Research, developing RTL code in Verilog and verification using SystemVerilog • Designed a Video Motion Estimator chip using Verilog and ... - Sep 28

Engineer Design

Lakewood, CA
... Professional Experience Semiconductor Consultant (November'2014 – Till date) As a Consultant, worked with Indian Institution Professor Publishing IEEE International Journals Papers on RTL Implementation and Simulation of (1) Low Power LFSR for BIST ... - Sep 27

Electrical Engineering Professional Experience

San Jose, CA
... 95112 Phone # (515)***-**** Email ID: acwr98@r.postjobfree.com LinkedIn: https://www.linkedin.com/in/venkata-rakesh-gudipalli-13a35841 SUMMARY 1 year of hands on experience of Verilog RTL, System Verilog, digital ASIC design, FPGA, computer ... - Sep 26

Data System

India
... I have to make sure that project is successfully accomplishing the task.RTL CODES USED VARIABLE OF SYSTEM VERILOG DATA TYPES, IN DIFFERENT PARTS OF TEST BENCH Firstly read the hardware specification, write ur verification plan start writing ur test ... - Sep 26

Design Computer Science

Rockville, MD
... Tools: Cadence Virtuoso, Encounter, Synopsys Design Compiler, Tetramax, Quartus II, Xilinx Vivado, Conformal ASIC Design flow: RTL Design/coding, Low Power Design, Synthesis, Verification, ATPG, DFT, STA, DRC, LVS Operating Systems: Windows, Linux ... - Sep 23

Engineer Design

San Jose, CA
... SKILLS SKILLS: SystemVerilog OOP, Verilog, UVM Methodology, Object-oriented language, HDL, Assertions (SVA), Coverage, RTL Design, IC Layout, ASIC Physical Design, VLSI, DRC, LVS, Digital Circuit Design, Static Timing Analysis, Low Power Design ... - Sep 21

Design Power

India
... Description : Designed finite state machine from design stage to GDS II Responsibilities: Architected the design Implemented RTL using Verilog HDL. Architected the class based verification environment using system Verilog Verified the RTL model ... - Sep 21

Design Project

India, Bengaluru, Karnataka
... Synthesis : RTL Compiler. ACADEMIC ACHIEVEMENTS: Got 1st prize, in HARDWARE EXPO during my UG, conducted by SPACE, MVGRCE. Received Merit Certificate and Scholarship for academic performance in M.Tech 1stsemister. PROJETS: 1.Design and functional ... - Sep 20
1 2 3 4 5 6 7 Next