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Engineer Electrical

Broomfield, CO
... Performed DO-254 Verification & Validation of FPGA RTL and mix signals circuits designs correcting: design requirements documentation, VHDL coding, board ground noise and identified EMC current spikes noise reduction from motor IGBT drivers using ... - Dec 01

Project Design

Tustin, CA
... oTop Level Simulation Test & Debug, Verilog (4 years), C programming (4 years) and RTL oFPGA (4 years), ARM 7, 8, 9 and 10. Technical Skills Programming: VHDL / Verilog HDL, PERL, System C, Vera, C, C++, keil C, Fortran, Assembly language. ... - Nov 30

Management Electrical Engineer

India, Chennai, Tamil Nadu
V.P.Sampath acxnbn@r.postjobfree.com Cell: +*19840163772 Summary: FPGA and ASIC RTL design for Communication Systems Simulation, Design Synthesis, Implementation, PAR, Timing Simulation Experience in FPGA prototyping of multi-million gate ASICs ... - Nov 25

Design Engineering

India, Pune, Maharashtra
... Eclipse Compute Platforms: Microsoft Windows, Linux, Apple Mac OS EMPLOYMENT EXPERIENCE Manuscript review editor for the IEEE Transactions on Reliability Since 2015 Engineer, Tenrehte Technologies, Inc., Rochester, NY Verilog RTL modeling and ... - Nov 21

Retail Management/Sales Management

Surprise, AZ
... two fundamental success factors to exceed guests’ expectations Train team members the value of accountability Work closely with RTL and the Optical Team in completing monthly store visit form for review Administer various facets of human resource ... - Nov 16

Teaching Associate.

Sacramento, CA
... VHDL, System Verilog Scripting Languages : Python, Perl, TCL Simulators : Simulink, PSpice, VCS Verilog Simulator, Spectre RTL Synthesis Tool : Synopsys Design Compiler FPGA’s & Version Control : Spartan 3E, DEO Nano (Cyclone IV), Git Operating ... - Nov 15

Digital design, Computer Architecture, RTL, Verilog

Sacramento, CA
... Wrote RTL code in Verilog HDL, and simulated in Synopsys VCS. Designed automated test bench for validating the data path. Did logic synthesis of the unit using Synopsys Design Compiler and generated timing and area reports. Code coverage was ... - Nov 15

Design Power

India, Bengaluru, Karnataka
... - SVA TB Methodology: UVM EDA Tool: Questasim and ISE, Modelsim Cadence Tool Suite (Virtuoso, Encounter, NC Launch, RC) Knowledge: RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis. ... - Nov 12

Customer Service Engineer

United States
... Supported GLS and RTL VTPSIM (Vector Test Pattern Simulation) for all CPD (Components Platform Division) and was tool owner for VTPSIM. Supported Design Engineering Environment for all Chipset Engineering, including Software and License ... - Nov 11

Design Test Cases

India, Bengaluru, Karnataka
... Role: Took the RTL from open cores and analyzed. Prepared the test plan. Prepared the test bench architecture. Test cases were verified. 2. Design and Verification of UART-APB. HDL: Verilog HDL. Verification Methodology: UVM. Tools Used: Libero, ... - Nov 11
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