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Engineer Electrical Engineering

Folsom, CA
... debug tools, logic design concepts and stimulators like VCS Hands on experience in UVM, assertions, Functional Coverage, RTL Designing, analysis of code coverage SKILLS Programming/Scripting languages: System Verilog, UVM, Python, Perl, Verilog, ... - Nov 22

Software Engineer Driver

Scottsdale, AZ
... Developed RTL for CPLD to update PCI interface Xilinx FPGA on the fly. Languages and Tools: C, GCC, GDB, bash, CVS, CrossTool, Verilog, Xilinx ISE Juniper Networks Inc., Sunnyvale, CA, Mar 2005 - Jan 2006 Consultant. Project: Network Security ... - Nov 22

Design Engineer Electrical Engineering

Marlborough, MA
... Experienced with RTL simulation & verification, designed layout of ADC, DAC, Audio amplifier, Transformer Circuit and MOSFET. Worked on low noise signal conditioning utilizing OPAMP, power managements, and various interfaces (I2C, SPI, Ethernet, CAN ... - Nov 22

Engineer Design

California
... For a FPGA design, a Fujitsu FPGA/ASIC design process was followed with a good RTL coding practice must have a default CASE statement, a mix of traditional Verilog and System Verilog (UVM) verification. Synopsis tools were for synthesis; errors and ... - Nov 19

Design Engineer

Chicago, IL
... RTL Design and Testbench verification of multiplier datapath (Verilog, Altera Quartus, Modelsim) Dec ‘15 Designed a datapath with components to perform 16 bit add-and-shift Booth multiplication, and a Moore-machine FSM in One hot style to control ... - Nov 17

Sap Test Cases

Austin, TX
... SAP QA Consultant Verified the availability of the SAP TAO agent for ABAP on the SAP server, Installation of Quality Center, SAP TAO client, Run Time Library (RTL), UI Scanner, QTP and requisite add-ins configured to execute tests. Created different ... - Nov 16

CFO

Lebanon
... RTL, & SEMINARS Microsoft and integration ATTENDED share point, F4B. FIDIC MEED Project Corporate mitigation, Advanced banking, Understanding causes, Doha Doha, HSBC Hospitals Lebanese Bank Qatar Bank for yearly Online finance Manama, financials ... - Nov 15

Design Engineer

Bengaluru, KA, India
... Expertise in Digital Design and Advanced Verification Techniques Proficient in RTL design, simulation and synthesis using Xilinx ISE, XST tools. Knowledgeable in CMOS VLSI design, Verilog RTL coding. Knowledgeable in ASIC front end/back end design. ... - Nov 14

Vhdl,Verilog,Basic C Language,Python,Perl.

AP, 531055, India
... Skills : Technical skills : Proficient in RTL design and simulation. Good in VHDL, Verilog HDL programing language. Knowledge in ASIC front end &back end design. Computer skills : Windows,linux Os. Computer basics. Hardware networking . Workshop : ... - Nov 14

ASIC Physical Design/Implementation Engineer

Plymouth, MN
... Eden Prairie, MN Responsible for all timing closure activities on their 40nm ultra low power ASIC Synopsys flow: DC-Graphical for RTL synthesis, ICC Place & Route, ICV, and PrimeTime/SI/PTPX for STA and Power estimation LSI/LSI Corporation/Avago ... - Nov 13
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