| Resume alert | Resumes 31 - 40 of 935 |
Internship Agricultural
Vasant Nagar, Karnataka, India
... CERTIFICATIONS: • VLSI Design using Verilog HDL-Webinar by MAVEN silicon • 2 nd South India Project Exhibition (SIPE-2K19) • Certificate of participation for online webinar on “Artifical intelligence for autonomous driving “by agimus technologies in ... - 2021 May 24
... CERTIFICATIONS: • VLSI Design using Verilog HDL-Webinar by MAVEN silicon • 2 nd South India Project Exhibition (SIPE-2K19) • Certificate of participation for online webinar on “Artifical intelligence for autonomous driving “by agimus technologies in ... - 2021 May 24
Collage Rv
Vasant Nagar, Karnataka, India
... EDUCATIONAL QUALIFICATION QUALIFICATION INSTITUTION UNIVERSITY/ BOARD YEAR OF PASSING PERCENTAGE PG DIPLOMA (VLSI) RV-VLSI RV 2019 - B.E in (Electronics And Communication Engineering) Akshaya Institute of Technology, Tumakuru. V.T.U Belgaum 2018 62% ... - 2021 May 24
... EDUCATIONAL QUALIFICATION QUALIFICATION INSTITUTION UNIVERSITY/ BOARD YEAR OF PASSING PERCENTAGE PG DIPLOMA (VLSI) RV-VLSI RV 2019 - B.E in (Electronics And Communication Engineering) Akshaya Institute of Technology, Tumakuru. V.T.U Belgaum 2018 62% ... - 2021 May 24
Internship Girl
Bangalore, Karnataka, India
... Verilog HDL Basics of PYTHON VLSI Skill Set: • Extrovert and comfortable in new environment. • Good communication and presentation skills Education: Secondary School Leaving Certificate Shree Sharada Girl’s High School, Ron Percentage: 80 % Pre ... - 2021 May 16
... Verilog HDL Basics of PYTHON VLSI Skill Set: • Extrovert and comfortable in new environment. • Good communication and presentation skills Education: Secondary School Leaving Certificate Shree Sharada Girl’s High School, Ron Percentage: 80 % Pre ... - 2021 May 16
Project Telugu
Vasant Nagar, Karnataka, India
... Professional Summary: ● Good knowledge on Digital Electronics and VLSI ASIC flow. ● DFT compiler on Scan Insertion at block level. ● DFT compiler on Compression at block level. ● Scan implementation plan at block level. ● Pattern generation using ... - 2021 May 15
... Professional Summary: ● Good knowledge on Digital Electronics and VLSI ASIC flow. ● DFT compiler on Scan Insertion at block level. ● DFT compiler on Compression at block level. ● Scan implementation plan at block level. ● Pattern generation using ... - 2021 May 15
Design Engineer Port
Vasant Nagar, Karnataka, India
... SKILLS Domain working in complete PD flow from RTL to GDSII Place and routing : Icc2_shell Platform :linux Good Knowledge on VLSI design and CMOS technology CHIP and Block level Floor planning, analysis of floorplan options taking into account timing ... - 2021 May 14
... SKILLS Domain working in complete PD flow from RTL to GDSII Place and routing : Icc2_shell Platform :linux Good Knowledge on VLSI design and CMOS technology CHIP and Block level Floor planning, analysis of floorplan options taking into account timing ... - 2021 May 14
Trainee Software Engineer,-C/C++& OOPs concept, HTML, JavaScript, Java
Vasant Nagar, Karnataka, India
... • Done internship at Semi-Conductors Laboratory and E&ICT Academy IIT Guwahati on Digital VLSI in Verilog Hardware Description Language. Duration: 4 months. • Done certification in Texas instruments for courses linear integrated circuits and ... - 2021 May 14
... • Done internship at Semi-Conductors Laboratory and E&ICT Academy IIT Guwahati on Digital VLSI in Verilog Hardware Description Language. Duration: 4 months. • Done certification in Texas instruments for courses linear integrated circuits and ... - 2021 May 14
Manual Testing Collage
Bangalore, Karnataka, India
... Educational Qualification R N S Institute Of Technology M Tech in VLSI and Embedded Systems CGPA – 8.5 2021 Bangalore Institute of Technology B E in Instrumentation Technology Percentage - 57.7 % 2016 Vijaya Composite P.U Collage II PUC Percentage - ... - 2021 May 13
... Educational Qualification R N S Institute Of Technology M Tech in VLSI and Embedded Systems CGPA – 8.5 2021 Bangalore Institute of Technology B E in Instrumentation Technology Percentage - 57.7 % 2016 Vijaya Composite P.U Collage II PUC Percentage - ... - 2021 May 13
Shah Android
Vasant Nagar, Karnataka, India
... Educational Qualifications: Board/Course Institution University/ Board Year of Passing % or CGPA of Marks MTech (Embeded System and VLSI Design) B.E(Instrume ntation and control) Chandubhai S Patel Institute of Technology Changa, Gujarat C.U. Shah ... - 2021 May 13
... Educational Qualifications: Board/Course Institution University/ Board Year of Passing % or CGPA of Marks MTech (Embeded System and VLSI Design) B.E(Instrume ntation and control) Chandubhai S Patel Institute of Technology Changa, Gujarat C.U. Shah ... - 2021 May 13
Trainee Embedded
Bangalore, Karnataka, India
... REVA University,Bengaluru,Karnataka,MTech in VLSI & Embedded Systems 2017-2019 with CGPA: 9.15 2. East Point College Of Engineering &Technology, Bengaluru-Karnataka, BE in Electronics and Communication Engineering 2013-2017 with 71.53% 3. Pre ... - 2021 May 13
... REVA University,Bengaluru,Karnataka,MTech in VLSI & Embedded Systems 2017-2019 with CGPA: 9.15 2. East Point College Of Engineering &Technology, Bengaluru-Karnataka, BE in Electronics and Communication Engineering 2013-2017 with 71.53% 3. Pre ... - 2021 May 13
Mnc Project
Vasant Nagar, Karnataka, India
... (VLSI Design & Embedded System) from Visvesvaraya Technological University, Belagavi, 2019 • B.E. (Electronics & Communication) from Visvesvaraya Technological University, Belagavi, 2017 PERSONAL PROFILE: • DOB :20-05-1996 • Address : Flat No.305 ... - 2021 May 13
... (VLSI Design & Embedded System) from Visvesvaraya Technological University, Belagavi, 2019 • B.E. (Electronics & Communication) from Visvesvaraya Technological University, Belagavi, 2017 PERSONAL PROFILE: • DOB :20-05-1996 • Address : Flat No.305 ... - 2021 May 13