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Verilog resumes in San Jose, CA

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Resume alert Resumes 41 - 50 of 447

Design Engineer Engineering

Los Gatos, CA
... •Delivered quality RTL codes using Verilog & synthesis tests using System Verilog for clock/power/pci-express units during final project milestone. Skills Project Management – Scheduling, resource planning, status tracking, risk mitigation, ... - 2020 Oct 06

Embedded/Firmware Engineer

Fremont, CA, 94536
... in Computer Science and Engineering, • GPA: 3.58, Dean’s Honors List- Fall 2016, Fall 2017, Winter 2018, Spring 2019, Winter 2020, Spring 2020 RELEVANT COURSES Intro to Digital Systems (System Verilog), Programming with Software Libraries (Python), ... - 2020 Aug 28

Design Engineering

San Jose, CA
... SKILLS: HDLs / HVLs: Verilog, SystemVerilog, JavaScript, Python Scripting, Object Oriented Programming (OOP). Methodology: UVM (Universal Verification methodology). Bus protocols: AMBA ARM AHB, APB, PCI. Simulation tools: Synopsys VCS, PrimeTime, ... - 2020 Aug 05

Engineer

San Jose, CA, 95135
... Visual Studio, Matlab, System Verilog VHDL RTL, Matlab, Xilinx ISE, Python 2.7. Reference • Upon your request - 2020 Aug 05

Engineer Electrical

San Jose, CA
... SKILLS Languages C, Python, CAPL script, Verilog, C++, microprocessor xx86 ALP Tools Vector CANalyzer, Peak, Intrepid NeoVI, TI Packet Sniffer, FMEA/HARA, Wireshark, EMI/EMC, Cadence, LabView. Lab Tool & Skills CANoe, Altium PCB, Oscilloscope, NI & ... - 2020 Jul 26

Design Engineering

Santa Clara, CA
... TECHNICAL SKILLS Hardware Description/ Programming/Scripting Languages: VHDL, Verilog HDL, System Verilog, Raspberry Pi, Python, Perl Design Tools: Cadence (Virtuoso, Encounter), Synopsys (DC Compiler, Formality), Calibre, LabView, Xilinx ISE. ... - 2020 Jul 13

Electrical Engineer Design

Santa Clara, CA
... that will help to evaluate the VLSI Design Verification Engineer SSR Labs – Pacifica, CA • To design and verify very large capacity memory systems using Verilog and System Verilog • Developing and modifying new design or verification IP. ... - 2020 Jul 06

Electrical Engineer Engineering

Union City, CA
... 2013 - June 2017 SKILLS C, C++, Python, MATLAB, LabView, Altium Designer, Eagle, CCS, Arduino, HSPICE, Synopsys, Cadence, Verilog, ADS, Circuits Lab Experience (oscilloscope, soldering station etc.) WORK EXPERIENCE Electrical Engineer, NASA Ames ... - 2020 Jun 27

Software Developer Engineer

Union City, CA
... Basic Knowledge of SPSS, VB6, Verilog and Pspice. • Database: SQL • Writing Skills: Technical Writing, Research, Editing. • MS Office: Word, Excel, Power Point EDUCATION • M.Tech – Manipal Institute of Technology [2016] Major: Biomedical Engineering ... - 2020 Jun 20

Engineer Design

San Jose, CA
... *System verilog OVM/UVM testbench development and modification. *Functional debug using cadence tools, source code debug using verdi. *Hardware Description Language : Verilog. *Programming Languages : Unix,C,perl,python Experience Intel Component ... - 2020 May 28
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