| Resume alert | Resumes 11 - 20 of 2012 |
Palo Alto Firmware Engineer
Menlo Park, CA
... FPGA Engineering Consultant November 2017 – November 2019 Digital architecture development from software baseline to optimized RTL code Developed and integrated peripheral interfaces for FPGA-to-CPU/sensor data communication • Multi-channel Direct ... - Mar 22
... FPGA Engineering Consultant November 2017 – November 2019 Digital architecture development from software baseline to optimized RTL code Developed and integrated peripheral interfaces for FPGA-to-CPU/sensor data communication • Multi-channel Direct ... - Mar 22
Electrical Engineering Mixed Signal
Tempe, AZ
... The output is the labeling of the nodes in the graph, which I implemented on System Verilog (RTL). In the next step, I created a script to convert my RTL implementation of a Neural Network into a synthesizable gate-level netlist. The script was run ... - Mar 19
... The output is the labeling of the nodes in the graph, which I implemented on System Verilog (RTL). In the next step, I created a script to convert my RTL implementation of a Neural Network into a synthesizable gate-level netlist. The script was run ... - Mar 19
Loan Officer Officers
Turlock, CA
... MTG RTL – Sales Support Assistant Bank of America Home Loans, Turlock, CA 06/09 – 04/10 Sales Support to the Mortgage Loan Officer and gives support to Fulfillment. Responsibilities include tracking loans, contacting clients for items needed, ... - Mar 13
... MTG RTL – Sales Support Assistant Bank of America Home Loans, Turlock, CA 06/09 – 04/10 Sales Support to the Mortgage Loan Officer and gives support to Fulfillment. Responsibilities include tracking loans, contacting clients for items needed, ... - Mar 13
Analog Layout Engineer
Cumming, GA
... Experiences in advanced technology node under 180nm/130nm/90nm/45nm/14nm/10nm/7nm/3nm &FinFET Proficient in PnR flow from RTL to GDS2 & Sign Off Activities Expert and accurate error fixing without drc in complex and congestive designs and Strong ... - Mar 10
... Experiences in advanced technology node under 180nm/130nm/90nm/45nm/14nm/10nm/7nm/3nm &FinFET Proficient in PnR flow from RTL to GDS2 & Sign Off Activities Expert and accurate error fixing without drc in complex and congestive designs and Strong ... - Mar 10
Front End Field Engineering
Sunnyvale, CA
... Citizen CAREER SUMMARY Over twenty years of experiences in low power, high performance, area efficient AI instruction set architectures, VLSI ASIC, ML, automotive, IoT physical designs, from RTL to GDSII semiconductor tape-out, electronic design ... - Mar 10
... Citizen CAREER SUMMARY Over twenty years of experiences in low power, high performance, area efficient AI instruction set architectures, VLSI ASIC, ML, automotive, IoT physical designs, from RTL to GDSII semiconductor tape-out, electronic design ... - Mar 10
C++ Computer Engineering
Stony Brook, NY
... of complex designs Optimized functional verification efficiency by validating, redesigning, and maintaining a Verilog-based RTL verification tool, resulting in a 30% reduction in verification time Projects Security-Enhanced Web Application for Real ... - Mar 09
... of complex designs Optimized functional verification efficiency by validating, redesigning, and maintaining a Verilog-based RTL verification tool, resulting in a 30% reduction in verification time Projects Security-Enhanced Web Application for Real ... - Mar 09
Front End Stack Developer
Phoenix, AZ
... SKILLS Languages: Typescript, Java, kotlin, PHP, cURL, graphQL, regex, bash, yml Frameworks: NextJS, Gatsby, React, React-Native, Node (Express), jQuery, Angular, Spring Boot, Laravel Libraries: babel, redux, jest / RTL, Storybook, i18next, formik ... - Mar 06
... SKILLS Languages: Typescript, Java, kotlin, PHP, cURL, graphQL, regex, bash, yml Frameworks: NextJS, Gatsby, React, React-Native, Node (Express), jQuery, Angular, Spring Boot, Laravel Libraries: babel, redux, jest / RTL, Storybook, i18next, formik ... - Mar 06
Program Management Project
Chicago, IL
... Deputy Director of Program Management ● Manage customer ASIC project from RTL to GDS including Package design, Post silicon to Mass Production. ● Involved in Customer project technical accessment to Project bidding. ● Planning milestone including ... - Mar 04
... Deputy Director of Program Management ● Manage customer ASIC project from RTL to GDS including Package design, Post silicon to Mass Production. ● Involved in Customer project technical accessment to Project bidding. ● Planning milestone including ... - Mar 04
Cruise Line First Cook
Depok, West Java, Indonesia
... Cook aboard MIRAY INTERNATIONAL, CRUISE LINE (GEMINI), 06 March 2019 - 22 October 2019 •Chef De Partie at LALLA RESTAURANT & RTL ( Regional Tasting Longue) Gatot Subroto, South Jakarta, 20 September 2017 - 01 June 2018 •Cook at RESTAURANT YAMAKAWA ... - Feb 29
... Cook aboard MIRAY INTERNATIONAL, CRUISE LINE (GEMINI), 06 March 2019 - 22 October 2019 •Chef De Partie at LALLA RESTAURANT & RTL ( Regional Tasting Longue) Gatot Subroto, South Jakarta, 20 September 2017 - 01 June 2018 •Cook at RESTAURANT YAMAKAWA ... - Feb 29
Mixed Signal Verification Engineer
Santa Clara, CA, 95050
... Functional verification of the RTL from top level full chip simulations with analog blocks modeled in Verilog-AMS or VHDL. Gate level simulations to identify timing related issues. Digital verification targeted towards full Functional and Code ... - Feb 21
... Functional verification of the RTL from top level full chip simulations with analog blocks modeled in Verilog-AMS or VHDL. Gate level simulations to identify timing related issues. Digital verification targeted towards full Functional and Code ... - Feb 21