| Resume alert | Resumes 61 - 70 of 386 |
Embedded Systems, Firmware Engineer, Hardware Engineer, Internship
San Jose, CA
... Coursework: Microprocessor and Microcontrollers, Advanced Computer Architecture, Digital Signal Processing, Verilog, FPGA, Embedded SoC Design, Machine Learning, Parallel Processors, CPU/GPU Architectures, PWM on Raspberry Pi 4, RISC- V(IGLOO2 ... - 2020 Mar 19
... Coursework: Microprocessor and Microcontrollers, Advanced Computer Architecture, Digital Signal Processing, Verilog, FPGA, Embedded SoC Design, Machine Learning, Parallel Processors, CPU/GPU Architectures, PWM on Raspberry Pi 4, RISC- V(IGLOO2 ... - 2020 Mar 19
Engineering Software Director Vice-President Development
Morgan Hill, CA
... Page 3 DAVID CAMPBELL ● Oversaw engineering division for all front-end systems products: design capture, simulation, FPGA system, PCB integration, parts library database system, and overall Cadence database framework. Development used C/C++ and ... - 2020 Jan 31
... Page 3 DAVID CAMPBELL ● Oversaw engineering division for all front-end systems products: design capture, simulation, FPGA system, PCB integration, parts library database system, and overall Cadence database framework. Development used C/C++ and ... - 2020 Jan 31
Manager Security
San Jose, CA
... kernel 2.6.10, 2.6.18 on Broadcom Sibyte, which is used for control plane processing and Cavium Octeon architecture, which is used for datapath processing, CDE (IPv4 and IPv6 Classification and Distribution Engine) and Verni FPGA (Xilinx) bringup. ... - 2019 Dec 02
... kernel 2.6.10, 2.6.18 on Broadcom Sibyte, which is used for control plane processing and Cavium Octeon architecture, which is used for datapath processing, CDE (IPv4 and IPv6 Classification and Distribution Engine) and Verni FPGA (Xilinx) bringup. ... - 2019 Dec 02
Software Engineer Manager
Fremont, CA
... The developed software packages include: - Ethernet Spanning Tree Protocol (IEEE802.1d), and LAN Bridge protocol (IEEE802.1d/1g) - ATM LLC multiplexing (rfc1483) - FPGA device drivers for DMA and wire speed packet or cell switching - Toshiba ATMo4 ... - 2019 Nov 04
... The developed software packages include: - Ethernet Spanning Tree Protocol (IEEE802.1d), and LAN Bridge protocol (IEEE802.1d/1g) - ATM LLC multiplexing (rfc1483) - FPGA device drivers for DMA and wire speed packet or cell switching - Toshiba ATMo4 ... - 2019 Nov 04
Electronics Engineer
Santa Clara, CA
... Electronic Laboratory Equipment: Oscilloscope, DC Power Supply, Function Generator, Digital Mulitmeter, LCR meter, Logic Analyzer, Network Analyzer, Curve Tracer, Spectrum Analyzer, microcontroller or FPGA development boards. MASTER’S PROJECT: A ... - 2019 Oct 10
... Electronic Laboratory Equipment: Oscilloscope, DC Power Supply, Function Generator, Digital Mulitmeter, LCR meter, Logic Analyzer, Network Analyzer, Curve Tracer, Spectrum Analyzer, microcontroller or FPGA development boards. MASTER’S PROJECT: A ... - 2019 Oct 10
Design Engineer Manufacturing
San Jose, CA
... •Design high speed Subsystems cover frequency ranges from 0.1 GHz to 40 GHz, low phase noise, high isolation, low RFI noise and performance with DDS, FPGA, CPLD •Design Four Channel MMW Translator converting frequency 47 GHz signal to C Band. CTT, ... - 2019 Oct 09
... •Design high speed Subsystems cover frequency ranges from 0.1 GHz to 40 GHz, low phase noise, high isolation, low RFI noise and performance with DDS, FPGA, CPLD •Design Four Channel MMW Translator converting frequency 47 GHz signal to C Band. CTT, ... - 2019 Oct 09
Engineer Design
San Jose, CA
... § Languages: TCL, VHDL, C, C++, JAVA, HTML § Technical Competencies: Physical verification flow, ASIC Design Flow, FPGA Design Flow, Timing Analysis, Multiple clock domain design, RF system architecture design, RTL level design and synthesis, Test ... - 2019 Aug 27
... § Languages: TCL, VHDL, C, C++, JAVA, HTML § Technical Competencies: Physical verification flow, ASIC Design Flow, FPGA Design Flow, Timing Analysis, Multiple clock domain design, RF system architecture design, RTL level design and synthesis, Test ... - 2019 Aug 27
Sales Manager
Saratoga, CA
... Strategically penetrated key customers in storage & semiconductor emerging markets including Solid State Drives (SSD) and Field Programmable Gate Arrays (FPGA). 1999 to 2004 entrego.com Redwood City, CA An Internet based portal solution designed to ... - 2019 Aug 14
... Strategically penetrated key customers in storage & semiconductor emerging markets including Solid State Drives (SSD) and Field Programmable Gate Arrays (FPGA). 1999 to 2004 entrego.com Redwood City, CA An Internet based portal solution designed to ... - 2019 Aug 14
Engineer Test
Sunnyvale, CA
... • Experience in ASIC verification, VIP development, Board bring-up, FPGA Emulation and System validation of embedded system. • Experience in verifying the Storage, DSP, Video, Consumer Electronics/Multimedia, Wireless domain ASICs • Worked with ... - 2019 Jul 10
... • Experience in ASIC verification, VIP development, Board bring-up, FPGA Emulation and System validation of embedded system. • Experience in verifying the Storage, DSP, Video, Consumer Electronics/Multimedia, Wireless domain ASICs • Worked with ... - 2019 Jul 10
Engineer Electrical
San Jose, CA
... TECHNICAL SKILLS Languages and/or HDL - Verilog, System Verilog, Perl, C++ EDA Tools - Synopsys VCS, Cadence Incisive, NCSim, Virtuoso, Spectre, Hspice, Xilinx ISE, ModelSim Operating Systems - Linux, Windows, macOS Familiarities – ASIC/FPGA design ... - 2019 May 14
... TECHNICAL SKILLS Languages and/or HDL - Verilog, System Verilog, Perl, C++ EDA Tools - Synopsys VCS, Cadence Incisive, NCSim, Virtuoso, Spectre, Hspice, Xilinx ISE, ModelSim Operating Systems - Linux, Windows, macOS Familiarities – ASIC/FPGA design ... - 2019 May 14