| Resume alert | Resumes 11 - 20 of 386 |
Project Management Manager
San Jose, CA
... ● Programming languages: C++, Java, Javascript, HTML/CSS, SQL, hardware description languages- Verilog, VHDL, FPGA. Volunteer and Additional Experiences ● Certified Scrum Master (CSM) ● Machine learning and business strategy certification 2024 ● ... - Feb 28
... ● Programming languages: C++, Java, Javascript, HTML/CSS, SQL, hardware description languages- Verilog, VHDL, FPGA. Volunteer and Additional Experiences ● Certified Scrum Master (CSM) ● Machine learning and business strategy certification 2024 ● ... - Feb 28
Verification Engineer Fpga Design
Santa Clara, CA, 95050
... Familiar with verification plan and coverage metrics Familiar with OOP constructs and constraint random verification 10+ years of experience with FPGA design and implementation, including verification, synthesis and P&R, STA, timing analysis and ... - Feb 06
... Familiar with verification plan and coverage metrics Familiar with OOP constructs and constraint random verification 10+ years of experience with FPGA design and implementation, including verification, synthesis and P&R, STA, timing analysis and ... - Feb 06
Technical Program Product Owner
San Jose, CA
... 5G Prototype: Generated input vectors, performed tests for Tx and FPGA interaction, and signal processing on Rx side for 1x1, 1x2, 2x1 and 2x2 MIMO. Skills required: C/C++, MATLAB, Verilog, and Perl. Mmwave MIMO: Performed tests for 1 user 1 stream, ... - Jan 16
... 5G Prototype: Generated input vectors, performed tests for Tx and FPGA interaction, and signal processing on Rx side for 1x1, 1x2, 2x1 and 2x2 MIMO. Skills required: C/C++, MATLAB, Verilog, and Perl. Mmwave MIMO: Performed tests for 1 user 1 stream, ... - Jan 16
Electrical Engineering System Design
San Jose, CA, 95126
... EXPERIENCE May 23 – Aug 23 Assistant System Engineering Trainee – Banking & Financial Solutions, TATA Consultancy Services, Bangalore ACADEMIC PROJECTS TITLE: IMAGE PROCESSING ON ZYNQ (FPGA) Objective was to input the image via Ethernet from a ... - Jan 10
... EXPERIENCE May 23 – Aug 23 Assistant System Engineering Trainee – Banking & Financial Solutions, TATA Consultancy Services, Bangalore ACADEMIC PROJECTS TITLE: IMAGE PROCESSING ON ZYNQ (FPGA) Objective was to input the image via Ethernet from a ... - Jan 10
Systems Engineer Project Management
Fremont, CA
... RF, Clock signals, controlled impedance, SMT, FPGA and thru-hole technology. Worked for electronic and mechanical packaging for numerous projects over the past nine years including the Orbital Maneuvering Vehicle (OMV) (space-based robot), Gamma-Ray ... - Jan 09
... RF, Clock signals, controlled impedance, SMT, FPGA and thru-hole technology. Worked for electronic and mechanical packaging for numerous projects over the past nine years including the Orbital Maneuvering Vehicle (OMV) (space-based robot), Gamma-Ray ... - Jan 09
Software Engineer C++
Milpitas, CA
... This involves FPGA Loading, CPLD Writing, and Flash writing through Cascon Galaxy, EEPROM writing through Test Stand. ● Developed Driver for DC Electronic Load. This involves programming of the GPIB interface using C. ● Development of Fixture driver ... - Jan 09
... This involves FPGA Loading, CPLD Writing, and Flash writing through Cascon Galaxy, EEPROM writing through Test Stand. ● Developed Driver for DC Electronic Load. This involves programming of the GPIB interface using C. ● Development of Fixture driver ... - Jan 09
Mixed Signal Design Engineer
Aptos, CA
... implementation and management of engineering projects Strong background in hardware (analog and mixed signal, digital ASIC and FPGA/PLD, front and back end), software, systems design and DSP, plant motion control systems and Lenze PLCs EDUCATION AND ... - 2023 Dec 01
... implementation and management of engineering projects Strong background in hardware (analog and mixed signal, digital ASIC and FPGA/PLD, front and back end), software, systems design and DSP, plant motion control systems and Lenze PLCs EDUCATION AND ... - 2023 Dec 01
Software Engineer United States
San Jose, CA
... • Pre-silicon debugging using JTAG on FPGA • Implemented IOMMU drivers • Various kernel bug fixes and improvements in kernel memory management area Various Personal/Home Projects Network Gadget/Utility Enthusiast/Hobbyist 1990 - October 2012 (22 ... - 2023 Nov 02
... • Pre-silicon debugging using JTAG on FPGA • Implemented IOMMU drivers • Various kernel bug fixes and improvements in kernel memory management area Various Personal/Home Projects Network Gadget/Utility Enthusiast/Hobbyist 1990 - October 2012 (22 ... - 2023 Nov 02
Design Engineer Rtl
San Jose, CA, 95118
... Transferred RTL from ASIC to FPGA for emulation. Verified data link layer for PCI-E. Used VIPs from Cadence, Synopsys Resolved LP related Multi-mode, Multi-corner MMMC, STA timing corners and PVT issues. Transformed verification components from OVM ... - 2023 Oct 31
... Transferred RTL from ASIC to FPGA for emulation. Verified data link layer for PCI-E. Used VIPs from Cadence, Synopsys Resolved LP related Multi-mode, Multi-corner MMMC, STA timing corners and PVT issues. Transformed verification components from OVM ... - 2023 Oct 31
Layout Designer Design
San Jose, CA
... Analog Switch design used to Supply a Photodiode · Lead in design of SoC Layout (wafer of 5mm X 5mm) · Collaboration with FPGA designers on SoC layout checking · Collaboration with detector of deep space team · Expertise in Modeling of an extremely ... - 2023 Oct 23
... Analog Switch design used to Supply a Photodiode · Lead in design of SoC Layout (wafer of 5mm X 5mm) · Collaboration with FPGA designers on SoC layout checking · Collaboration with detector of deep space team · Expertise in Modeling of an extremely ... - 2023 Oct 23