| Resume alert | Resumes 1 - 9 of 9 |
Trainee - Advanced VLSI Design and Verification
Guntur, Andhra Pradesh, India
... Good at FPGA front end design RTL coding techniques. Good at writing Test benches using System Verilog and UVM Very good knowledge in verification methodologies. SKILLS VLSI Domain Skills HDL : Verilog HVL : System Verilog Verification Methodology : ... - 2021 Feb 12
... Good at FPGA front end design RTL coding techniques. Good at writing Test benches using System Verilog and UVM Very good knowledge in verification methodologies. SKILLS VLSI Domain Skills HDL : Verilog HVL : System Verilog Verification Methodology : ... - 2021 Feb 12
Engineering Health
Vijayawada, Andhra Pradesh, India
... Attended a 3 days workshop on VLSI FPGA Programming organized by the department of electronics and communication engineering. Attended a 3 days workshop on quadcopter at Pydah college of engineering organized by SKYFI labs. Extra curricular ... - 2021 Jan 31
... Attended a 3 days workshop on VLSI FPGA Programming organized by the department of electronics and communication engineering. Attended a 3 days workshop on quadcopter at Pydah college of engineering organized by SKYFI labs. Extra curricular ... - 2021 Jan 31
Assistant Electrical
Vijayawada, Andhra Pradesh, India
... “A Reduced Switching Stress and High Efficiency of FPGA Based IBSPFC and QSC Based IBSPFC for LED and Energy Storage Systems.” Accepted for publication in Journal European des Systems Automatises.( Free Scopus Indexed) S.L.V Sravan kumar, Dr.N Ravi ... - 2020 Dec 31
... “A Reduced Switching Stress and High Efficiency of FPGA Based IBSPFC and QSC Based IBSPFC for LED and Energy Storage Systems.” Accepted for publication in Journal European des Systems Automatises.( Free Scopus Indexed) S.L.V Sravan kumar, Dr.N Ravi ... - 2020 Dec 31
Design Engineering
Vijayawada, Andhra Pradesh, India
... Road,One Town, Vijayawada, Andhra Pradesh LinkedIn ID- https://www.linkedin.com/in/kaja-nagendra-6777a616a Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2020 Dec 10
... Road,One Town, Vijayawada, Andhra Pradesh LinkedIn ID- https://www.linkedin.com/in/kaja-nagendra-6777a616a Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2020 Dec 10
Assistant Project Coordinator
Vijayawada, Andhra Pradesh, India
... “A Reduced Switching Stress and High Efficiency of FPGA Based IBSPFC and QSC Based IBSPFC for LED and Energy Storage Systems.” Accepted for publication in Journal European des Systems Automatises.( Free Scopus Indexed) S.L.V Sravan kumar, Dr.N Ravi ... - 2020 Nov 18
... “A Reduced Switching Stress and High Efficiency of FPGA Based IBSPFC and QSC Based IBSPFC for LED and Energy Storage Systems.” Accepted for publication in Journal European des Systems Automatises.( Free Scopus Indexed) S.L.V Sravan kumar, Dr.N Ravi ... - 2020 Nov 18
Engineering Security
Guntur, Andhra Pradesh, India
... PERSONAL PROJECTS Password based door locking system (01/2019 – 04/2019) Theft-proof,more secure than old locks High Security Door Lock System Benefits Reduce Costs in the Long Run FPGA implementation of arithmetic generator for POSIT number system ... - 2020 Sep 06
... PERSONAL PROJECTS Password based door locking system (01/2019 – 04/2019) Theft-proof,more secure than old locks High Security Door Lock System Benefits Reduce Costs in the Long Run FPGA implementation of arithmetic generator for POSIT number system ... - 2020 Sep 06
Electrical Engineer
Vijayawada, Andhra Pradesh, India
... Engineering Intern: 8/17 – 8/18 Artesyn Tempe, AZ • Responsible for analyzing the architecture and design of various FPGA’s for direct and third-party clients. • Created Tests and test Environment to meet the design specifications using LabVIEW. • ... - 2020 Jul 26
... Engineering Intern: 8/17 – 8/18 Artesyn Tempe, AZ • Responsible for analyzing the architecture and design of various FPGA’s for direct and third-party clients. • Created Tests and test Environment to meet the design specifications using LabVIEW. • ... - 2020 Jul 26
VLSI engineer with good knowledge of digital systems
Vijayawada, AP, India
... The main objective of this project is to show various software applications of AES algorithm and AES implementations on an Field Programmable Gate Array (FPGA), a 128-bit AES encryption and decryption using Rijndael Algorithm is designed and ... - 2015 Jul 08
... The main objective of this project is to show various software applications of AES algorithm and AES implementations on an Field Programmable Gate Array (FPGA), a 128-bit AES encryption and decryption using Rijndael Algorithm is designed and ... - 2015 Jul 08
Verilog, VHDL, C, Physical Design, RTL synthesis/Coding
Vijayawada, AP, India
... Good Understanding of the ASIC and FPGA Design flow and Digital Design. Worked on the Digital as well as analog and high speed VLSI circuits Designs with Verilog for logic implementation and Xilinx ISE Tool for Simulation and Synthesis. Proficient ... - 2014 Sep 09
... Good Understanding of the ASIC and FPGA Design flow and Digital Design. Worked on the Digital as well as analog and high speed VLSI circuits Designs with Verilog for logic implementation and Xilinx ISE Tool for Simulation and Synthesis. Proficient ... - 2014 Sep 09