| Resume alert | Resumes 1 - 10 of 56 |
Project Management Product Development
Pune, Maharashtra, India
... The motor is controlled using FPGA interface for each motion block containing 4 axes each. ●HW design with required interfaces ●Client support for acceptance testing as per defense standards Project: Range Finder Camera Client: US client Environment ... - Apr 06
... The motor is controlled using FPGA interface for each motion block containing 4 axes each. ●HW design with required interfaces ●Client support for acceptance testing as per defense standards Project: Range Finder Camera Client: US client Environment ... - Apr 06
Mini Project Engg
Pune, Maharashtra, India
... TECHNICAL SKILLS: DESIGNING SOFTWARES KNWOLEDGE: NI Multisim Xilinx & Proteus PROGRAMING SOFTWARE KNOWLEDGE: C LANGUAGE, DATA STRUCTURE, MATLAB, FPGA, NI LABVIEW, Assembly Language: 8051, Embedded C, Python, VHDL, Verilog. PROJECTS: Designed ... - 2021 Dec 07
... TECHNICAL SKILLS: DESIGNING SOFTWARES KNWOLEDGE: NI Multisim Xilinx & Proteus PROGRAMING SOFTWARE KNOWLEDGE: C LANGUAGE, DATA STRUCTURE, MATLAB, FPGA, NI LABVIEW, Assembly Language: 8051, Embedded C, Python, VHDL, Verilog. PROJECTS: Designed ... - 2021 Dec 07
C, Python, Verilog, Quality Assurance, Testing
Pune, Maharashtra, India
... 4) Boards: FPGA (Xilinx Spartan 3E and Zybo Z10), iMX8M (PCIE-UART, SD-SD, SD-UART) 5) BUS Protocols: I2C, SPI EDUCATION: 1) Master of Technology • 2019 - 2021 • NIT Kurukshetra Embedded System Design with current CGPA of 8.88 2) Bachelor of ... - 2021 May 20
... 4) Boards: FPGA (Xilinx Spartan 3E and Zybo Z10), iMX8M (PCIE-UART, SD-SD, SD-UART) 5) BUS Protocols: I2C, SPI EDUCATION: 1) Master of Technology • 2019 - 2021 • NIT Kurukshetra Embedded System Design with current CGPA of 8.88 2) Bachelor of ... - 2021 May 20
Vellore Designer
Pune, Maharashtra, India
... TECHNICAL SKILLS Programming: C, C++, Python, basic Data Structure, FPGA (VHDL Programming). Design Software Tools: Arduino IDE, Energia IDE, Keil Micro vision, Dev c++, Vivado, Spyder, Anaconda. Design Hardware Tool: DipTrace Launcher (PCB Design) ... - 2021 May 13
... TECHNICAL SKILLS Programming: C, C++, Python, basic Data Structure, FPGA (VHDL Programming). Design Software Tools: Arduino IDE, Energia IDE, Keil Micro vision, Dev c++, Vivado, Spyder, Anaconda. Design Hardware Tool: DipTrace Launcher (PCB Design) ... - 2021 May 13
Office Project
Pune, Maharashtra, India
... Brief:IthasperipheralslikeVirtex4 FPGA,ADC,Video Interfaces,SRAM,MemoryFlash,EEPROM,Serialinterfaces etc. Role:Ihave done IO planning,FPGA selection,power calculation,powersystemdesign,interfacingofperipherals, testingofFPGAboard. TITLE ... - 2021 Mar 06
... Brief:IthasperipheralslikeVirtex4 FPGA,ADC,Video Interfaces,SRAM,MemoryFlash,EEPROM,Serialinterfaces etc. Role:Ihave done IO planning,FPGA selection,power calculation,powersystemdesign,interfacingofperipherals, testingofFPGAboard. TITLE ... - 2021 Mar 06
Project Engineering
Pune, Maharashtra, India
... battery,etc Project name 2) design an uart analyzer using fpga board (Be current) Description:In 4th year we are doing a sponsered project in VLSI technology using fpga and uart and this project can be used in future also for communication purpose. ... - 2021 Feb 22
... battery,etc Project name 2) design an uart analyzer using fpga board (Be current) Description:In 4th year we are doing a sponsered project in VLSI technology using fpga and uart and this project can be used in future also for communication purpose. ... - 2021 Feb 22
Engineering Safety
Pune, Maharashtra, India
... SEMINAR PRESENTED Seminar presented on “3D FPGA VS MULTIPLE FPGA” in Bachelor of Engineering in Electronics and Telecommunication held at JDIET on 6 Aug 2016. PROJECTS BE. Major project --- “REAL TIME HEALTH MONITORING SYSTEM Technology Used: ... - 2021 Feb 13
... SEMINAR PRESENTED Seminar presented on “3D FPGA VS MULTIPLE FPGA” in Bachelor of Engineering in Electronics and Telecommunication held at JDIET on 6 Aug 2016. PROJECTS BE. Major project --- “REAL TIME HEALTH MONITORING SYSTEM Technology Used: ... - 2021 Feb 13
Design Engineer
Pune, Maharashtra, India
... SGGS IE & T, Nanded 2017 6.96 H.S.C Science Maharashtra State Board 2013 76.17% S.S.C General Maharashtra State Board 2011 78.55% >>KeySkills Programming Languages : C, Embedded C(CCS), Digital design, FPGA. VLSI Programming : Pspice, ngspice, ... - 2021 Feb 12
... SGGS IE & T, Nanded 2017 6.96 H.S.C Science Maharashtra State Board 2013 76.17% S.S.C General Maharashtra State Board 2011 78.55% >>KeySkills Programming Languages : C, Embedded C(CCS), Digital design, FPGA. VLSI Programming : Pspice, ngspice, ... - 2021 Feb 12
Engineering Software Developer
Pune, Maharashtra, India
... This project consists of a fully IMX6 Soc based project with FPGA, AFE board, ultrasound transducer and pressure sensor. This is a single channel (Single Ultrasound Transducer) project with camera and display with user specific button functionality ... - 2021 Feb 09
... This project consists of a fully IMX6 Soc based project with FPGA, AFE board, ultrasound transducer and pressure sensor. This is a single channel (Single Ultrasound Transducer) project with camera and display with user specific button functionality ... - 2021 Feb 09
Engineer Design
Pune, Maharashtra, India
... • Basics of shell script programming HDL: • Verilog Verification Language: • Sound Knowledge System Verilog(SV) • Basic Knowledge of UVM Operating Systems: • Windows • Linux Tools Known: • For Simulation: o ModelSim -Intel FPGA starter Edition 10.5c ... - 2021 Feb 08
... • Basics of shell script programming HDL: • Verilog Verification Language: • Sound Knowledge System Verilog(SV) • Basic Knowledge of UVM Operating Systems: • Windows • Linux Tools Known: • For Simulation: o ModelSim -Intel FPGA starter Edition 10.5c ... - 2021 Feb 08