Design Engineer

***E, **rd Street, Apt**** Yongbo Fu *****@****.***.***

Chicago, IL, 60616 312-***-****

Objective

A very creative and ambitious young man equipped with solid digital and analog circuit design, VHDL hands on experiences, looking for a position in a fast pace group.

Education

Illinois Institute of Technology Expected Graduation 2012.12

Master of Science in Electrical Engineering

Harbin Engineering University

Bachelor in Electrical Engineering with honors of the third level prize scholarship and a prize of golden ideas innovation competition. 2006.9 2010.7

Bachelor in Business Administration 2007.9 2009.7

Technical Skills

Programming languages: Python, Verilog, VHDL, C, C++, Assembly Language, JAVA tcl/tk;

Applications: Modelsim, Hspice, Protel, Matlab, MS Office applications, Ulead VideoStudio;

Mobile Device Testing Tools: Anite, SAS/SASLite, PCOM, IT3-MOVE, RSD General, RadioComm, Motorola Test Central

ERP software of UFIDA U-8;

Technical Experiences

Product test engineer in Motorola Mobility

2011.5-2012.8

Technical test for Motorola GSM cellular handsets validation for AT&T

Experience using Anite, Rohde Schwarz for carrier validation

Setting up of racks for Automation testing for mobile devices. Checking all the logs from the automation and find the failure then report them to JIRA with detailed information.

Test Development for Manual testing using Motorola Test Central.

Planning of test case, test plans and test suites and execution of them.

Reporting results for the verification and validations of Motorola mobile devices.

Defect reporting and tracking using tools like Edart, Jira and BUGZILLA.

Working closely with Development team to log requirements for the generated defects.

Interacting with vendors, collect updates and create and build an image which includes all updated features and executing the test plan.

Serving in user trial for data collection of MOTOACTV device.

C programmer for a pointer clock system based on single-chip computer 2010.2-2010.6

Hardware and arithmetic design for the whole circuit. Calculate the time delays and make the single LED composed round clock screen functions well by controlling the single-chip computer and the I/O intention chips.

Reading and understanding the functions of the instruments used in the circuit in C and assembly languages.

Writing the C program for the whole system;

Design and Synthesis of Central Processing Units using verilog 2010.10-2010.11

Design the arithmetic for 32-bit CPUs with carry ripple adder and carry look ahead adder in ALUs

Writing the Verilog HDL program for the CPU and translate the verification program which is in assembly language into machine language using Espresso.

Verification of the design using SUE, Hspice, Magic and Gemini.

Course Projects

Design and simulation of a required 32-bit CPU, cache, bus and memory datapath system using VHDL 2011.3-2011.4

Decimal Arithmetic Algorithms and Implementation for High Speed Computer Arithmetic: compare four related papers in this field. 2010.11-2010.12

CAD Tool Design for Static Timing Analysis: 2010.11-2010.12

C program for realizing Time Slack Analysis

Tcl/Tk program for an optimized gate-level design using cell swapping.

Multiplexer design using VHDL program. 2011.1-2011.2

Other Experiences

New students orientation leader of Illinois Institute of Technology 2011.6-2011.8

Volunteer of IIT homecoming event 2011.9

Volunteer of 2011 Chicago City Marathon 2011.10.9

Career fair assistant in Illinois Institute of Technology. 2011.2.24

Travel counselor at Check: Europe Travel Inc. 2010.9-2011.2

Leader of a student oral English association in university. 2007.5-2010.4

Hobbies

Swimming, traveling, photographing.

Contact this candidate