Project High School

VINEELA CHAVADA

H.no: **-**, Kanigiri, *******.*******@*****.***

Prakasam Dist, +91-784*******

Andhra Pradesh.

OBJECTIVE

To obtain a position that leverages my creative problem solving ability, leadership skills, and desire for continued learning.

WORK EXPERIENCE:

I have 9 months experience as an Intern on development domain for the project “Optical Network Terminal-Automation Setup” in Alcatel Lucent pvt Ltd,Chennai from September 2nd- 2011 to May 31st,2012.

EDUCATION

M.Tech in VLSI -Design 7.9/10.00 July 2010-May2012

Vellore Institute of Technology

B.Tech in Electronics &Instrumentation 72.4% Sept 2005-May 2009 Prakasam Engineering College

Intermediate 76.9% July 2003-April 2005

Nethaji Junior College,

Secondary School Certificate 87% July 2005-March 2009

VCA Govt. High School,

ACADEMIC PROJECTS

M.Tech(1st Semester):

Project Title: Implementation Of MAC Unit For DSP Applications

Duration: 3 Months

Description: This project proposes the Efficient MAC Unit implementation using fastest Multiplier in-order to achieve high performance digital processing system (DSP) using Xilinx ISE simulator, Verilog HDL and Model SIM Simulator.

M.Tech(2nd Semester):

Project Title: LOGIC BIST SYNTHESIS USING OPTIMIZED 2D-LFSR FOR CORE BASED DESIGNS

Duration: 3 Months

Description: This Project explains the Testing and Verification of Logic BIST Synthesis and fault coverage of Circuit Under Test (CUT) using Hardware pattern generators of 2D-LFSR on SOC with HDL Coding . The Test case patterns are generated using DFT Advisor tool and simulation done in Xilinx ISE Simulator.

M.Tech(2nd Semester):

Project Title: DESIGN OF A GYMBYKE -CONTROLLER FROM THE SPECIFICATIONS

Duration: 3 Months

Description: The Gym-Byke Controller is designed based on the specifications of appropriate Mode selection and Effort level selection. HDL coding is done in Verilog based on the state machine diagram. Simulation is done using Cadence Nc-Sim tool. Synthesis of the HDL file is done using Cadence RTL compiler. Backend process is done using Cadence Soc-Encounter .

B.Tech(8th Semester):

Project Title: SMART SOLAR TRACKING SYSTEM FOR OPTICAL POWER GENERATION

Duration: 6 Months

Description: The project proposes implementation of embedded system with servo motor controller to track the sun direction through solar panel and utilize this energy for home and industry applications.

B.Tech(6th Semester):

Project Title: AUTOMATIC TRAFFIC LIGHT CONTROLLER

Duration: 3 Months

Description: The project proposes the design of Micro controller to transfer data and display situation of detector by using LED with-in time limit.

TECHNICAL SKILLS

HDL Known : Verilog

Functional Verification Tool : Modelsim, NC- Sim (Cadence), XILINX ISE 10.2i

Synthesis tool : RTL-Compiler (Cadence)

Back end Tools : SOC Encounter (Cadence)

Layout Tool’s : IC Station (Mentor graphics)

Languages : C,Perl

EXTRA CURRICULAR ACTIVITIES

• Participant of NSS campaign in Nethaji Intermideate college

• Published paper on “Implementation Of MAC Unit For DSPApplications” in V.I.T International SET Conference 2010.

• Published paper on “LOGIC BIST SYNTHESIS USING OPTIMIZED 2D-LFSR FOR CORE BASED DESIGNS” in V.I.T International SET Conference 2011

PERSONAL PROFILE

Date of Birth : 15-08-1988

Father’s Name : Ch.Malakonda Reddy

Gender : Female

Languages Known : English, Hindi, Telugu.

Hobbies : Listening Songs,Saree painting

Marital Status : Single

Nationality : Indian

DECLARATION

I here by declare that the above furnished details are true and genuine to the best of my knowledge.

(Vineela Ch)

VINEELA CHAVADA

H.no: 10-15, Kanigiri, *******.*******@*****.***

Prakasam Dist, +91-784*******

Andhra Pradesh. +91-720*******

OBJECTIVE

To obtain a position that leverages my creative problem solving ability, leadership skills, and desire for continued learning.

WORK EXPERIENCE:

I have 9 months experience as an Intern on development domain for the project “Optical Network Terminal-Automation Setup” in Alcatel Lucent pvt Ltd,Chennai from September 2nd- 2011 to May 31st,2012.

EDUCATION

M.Tech in VLSI -Design 7.9/10.00 July 2010-May2012

Vellore Institute of Technology

B.Tech in Electronics &Instrumentation 72.4% Sept 2005-May 2009 Prakasam Engineering College

Intermediate 76.9% July 2003-April 2005

Nethaji Junior College,

Secondary School Certificate 87% July 2005-March 2009

VCA Govt. High School,

ACADEMIC PROJECTS

M.Tech(1st Semester):

Project Title: Implementation Of MAC Unit For DSP Applications

Duration: 3 Months

Description: This project proposes the Efficient MAC Unit implementation using fastest Multiplier in-order to achieve high performance digital processing system (DSP) using Xilinx ISE simulator, Verilog HDL and Model SIM Simulator.

M.Tech(2nd Semester):

Project Title: LOGIC BIST SYNTHESIS USING OPTIMIZED 2D-LFSR FOR CORE BASED DESIGNS

Duration: 3 Months

Description: This Project explains the Testing and Verification of Logic BIST Synthesis and fault coverage of Circuit Under Test (CUT) using Hardware pattern generators of 2D-LFSR on SOC with HDL Coding . The Test case patterns are generated using DFT Advisor tool and simulation done in Xilinx ISE Simulator.

M.Tech(2nd Semester):

Project Title: DESIGN OF A GYMBYKE -CONTROLLER FROM THE SPECIFICATIONS

Duration: 3 Months

Description: The Gym-Byke Controller is designed based on the specifications of appropriate Mode selection and Effort level selection. HDL coding is done in Verilog based on the state machine diagram. Simulation is done using Cadence Nc-Sim tool. Synthesis of the HDL file is done using Cadence RTL compiler. Backend process is done using Cadence Soc-Encounter .

B.Tech(8th Semester):

Project Title: SMART SOLAR TRACKING SYSTEM FOR OPTICAL POWER GENERATION

Duration: 6 Months

Description: The project proposes implementation of embedded system with servo motor controller to track the sun direction through solar panel and utilize this energy for home and industry applications.

B.Tech(6th Semester):

Project Title: AUTOMATIC TRAFFIC LIGHT CONTROLLER

Duration: 3 Months

Description: The project proposes the design of Micro controller to transfer data and display situation of detector by using LED with-in time limit.

TECHNICAL SKILLS

HDL Known : Verilog

Functional Verification Tool : Modelsim, NC- Sim (Cadence), XILINX ISE 10.2i

Synthesis tool : RTL-Compiler (Cadence)

Back end Tools : SOC Encounter (Cadence)

Layout Tool’s : IC Station (Mentor graphics)

Languages : C,Perl

EXTRA CURRICULAR ACTIVITIES

• Participant of NSS campaign in Nethaji Intermideate college

• Published paper on “Implementation Of MAC Unit For DSPApplications” in V.I.T International SET Conference 2010.

• Published paper on “LOGIC BIST SYNTHESIS USING OPTIMIZED 2D-LFSR FOR CORE BASED DESIGNS” in V.I.T International SET Conference 2011

PERSONAL PROFILE

Date of Birth : 15-08-1988

Father’s Name : Ch.Malakonda Reddy

Gender : Female

Languages Known : English, Hindi, Telugu.

Hobbies : Listening Songs,Saree painting

Marital Status : Single

Nationality : Indian

DECLARATION

I here by declare that the above furnished details are true and genuine to the best of my knowledge.

(Vineela Ch)

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