ASIC design/PHY design/RTL design/Verification/4.5 years

Sandeep Ramakrishnan

***, ******* ****, *** ****** 1,

Bangalore, India

**.*******@*****.***, Phone: +919*********

Industrial Experience

Working as Staff Engineer,IC Design at Broadcom India from Nov 2010 to till date

Worked as ASIC Design Engineer, at Wipro Technologies for 3 years 1 month

Education:

College of Engineering, Kerala University, India

• B.Tech Electronics and Communication Engineering, Aug 2003- Jun 2007

Experience Summary

4.5 years of experience in the digital front end design activities

Experience in development of LTE PHY

Experience in development of WLAN PHY

Knowledge of wireless communication and digital signal processing

Involved in the complete development cycle of 2 SoCs from spec to tape-out

Very good understanding of SoC architecture

Strong knowledge of ARM processor architecture

RTL integration on ARM processor based SoCs

Good logic/digital design skills

Good RTL coding skills

Good Experience in Synthesis

Experience in Formal Verification

Strong knowledge of STA concepts

Expert in RTL and Gate level simulations

TDL based simulations for Post Silicon validation

Very good at Perl/Tcl scripting

Skills

HDLs : Verilog, VHDL, SystemC

Verification Languages : C/C++,Assembly(ARM)

Protocols : AHB, AXI, USB

Processors : CortexM3, CortexR4

Signal Processing : MATLAB

Synthesis : Design Compiler

HLS : Forte Cynthesizer

Simulators : NCSim, VCSMX

Formal Verification : Conformal LEC

Lint Tools : SpyGlass

Scripting Languages : Perl, TCL, Shell, Awk

Revision Control : Clearcase, CVS

Debugger : Verdi

Project Details

1. Turbo Decoder (Broadcom)

Role : Architect, Design Engineer

Language : SystemC

HLS tool : Forte Cynthesizer

Responsibilities

Architecture the Turbo Decoder block

Coding of sub blocks in SystemC

Synthesis of SystemC code using Forte Cynthesizer

Area optimization

2. Area Optimization of LTE PHY (Broadcom)

Role : Design Engineer

Language : Verilog

Responsibilities

Work with architects to explore options to reduce the area of LTE PHY

Synthesis of PHY

Optimization of Time domain processing block of PHY, which interfaces with ADC/DAC

Optimization of Maximum Likelihood decoder block

Study of Viterbi decoder and Turbo decoder

3. Development of WLAN PHY (Broadcom)

Role : Design and Verification Engineer

Language : VHDL

Responsibilities

Design and Verification of frequency domain scaling block for OFDM subcarriers

Verification of Power Amplifier PreDistortion compensation and calibration blocks

4. CPU Compare Module ( Wipro Technologies )

Role : RTL Design Engineer

Language : Verilo

Responsibilities

Micro architectural specification development

Design partitioning

RTL development in verilog

Synthesis using Design Compiler

5. Soc targeted for electronic braking system ( Wipro Technologies )

Role : Verification Engineer

Technology : 65nm

Responsibilities

Simulation setup creation for RTL & Gate level simulations

Verification of GPIO, PLL wrapper, MBIST blocks

Block level synthesis

Writing system level testcases

Achievements

1. Introduced the concept of tester optimized testcases and reduced Post silicon functional test time by 30%

2. Got appreciation from end customer for writing a tcl script, which displays the current instruction being executed by ARM processor.

6. SoC for automotive dash board display ( Wipro Technologies )

Role : Design Engineer

Technology : 65nm

Responsibilities

RTL development of Pin Multiplexing block

Testbench development for Camera subsystem

Integration of Camera subsystem & Display controller blocks

Synthesis of Camera subsystem & Display controller modules

RTL and Gate level verification of the above two blocks

Personal Details

Name: Sandeep R.K

Date of Birth: 30-05-1986

Nationality: Indian

Marital Status: Single

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