Design Electrical

Sarath Chandra Grandhi

**** ********* ******, #**, *** Angeles, CA 90007 (M) 681-***-**** **************@*****.**.**

Objective

Seeking a challenging position in the field of Mixed-Signal IC Design and Verification, Digital Circuit Design and Verification.

Education

Master of Science in Electrical Engineering Spring 2012 (GPA 3.4)

University of Southern California, Los Angeles

Bachelor of Engineering in Electrical & Electronics May 2009 (GPA 4.0)

Osmania University, India (Gold Medalist)

Relevant Courses

Advanced VLSI System Design Advanced Mixed Signal IC Design CMOS VLSI Design Analog IC Design

VLSI System Design Mixed Signal IC Design Computer Systems Organization

Technical Skills

Tools: Cadence Virtuoso, ModelSim, Tanner Tools, LTSpice, NanoSim, HSPICE, MATLAB

Languages: C, C++, Verilog

Experience

Analog Engineering Intern, Conexant Systems, India July 2009 –July 2010

Designed and carried Pre silicon verification for a Low Drop out Regulator for Handheld applications. Implemented the schematic in Cadence.

Converts external voltage (nominally 5.0V) to 3.30V regulated output capable of up to 125ma load current.

Additionally supplies external power for devices such as an optical interface chip, radio chip.

USC Grader : VLSI System Design, EE 577a under Dr Shahin, Nazarian Spring 2012

MOS VLSI Design, EE 477L under Dr Shahin Nazarian Fall 2011

Projects

Design of 8-bit, 1GS/s Two-Step Flash ADC in ASU CMOS 45nm model

Design includes Sample and Hold Circuit, Regenerative Latch Based Comparators, DAC, Switched capacitor Subtractor.

Designed a power efficient ADC that consumes power of 39mW, FOM 6.43 pJ/conversion with 250 MS/S.

Time Interleaving is done to achieve the speed requirement of 1GS/S and tested for performance parameters in Cadence.

256 bit SRAM Design in 0.18um tech

Schematic, layout extraction, place and route, LVS of SRAM with 4*16 row decoder, precharge, read/write circuitry, and sense amplifiers using cadence virtuoso, spectre and HSPICE. Total read speed of 1.12ns and write speed of 972.5 ps.

High-speed, High-Gain, Low-Power, Low-voltage CMOS Operational Amplifier design

Designed an op-amp which is a part of a high-speed data converter circuit used in Imaging Sensor products.

State-of-the-art 2-stage op-amp with 100dB gain, UGB 1GHz, Low Power<50mW Folded Cascode topology using IBM90nM.

Hardware Design of Serializer Deserializer

Schematic, floor planning, layout design of a simplified SerDes used in Serial on-chip communication in 0.18um tech using 256 bit data memory using SRAM,16 bit Carry Select Adder, Serializer, Deserilializer and Repeater.

Network on Chip 2D Mesh Router Design (Current Project)

RTL Design (in Verilog), Simulation in Cadence NC-Sim, Synthesis using Design compiler, Conformal, Static Timing Analysis using Prime time, Place and Route using SOC Encounter.

Arbiter for System on Chip Packet Routing

Designed a 2-1 Arbiter to achieve fair arbitration for two 4-bit Data transmitters.

Implemented the schematic, layout extraction, place and route, LVS and DRC in Cadence Environment.

Five Stage Pipelined MIPS CPU architecture

Designed five Stage pipelined CPU architecture using RTL coding with early branch supporting a subset of MIPS Instruction set. Implemented Hazard Detection Unit and Forwarding Unit to eliminate data dependency hazards.

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