Engineer Design

Edmond Barakat

*** ********** **.

Marlton NJ. **053

Home 856-***-****

Cell: 610-***-****

Email: *********@***.***

Experience Summary:

Highly motivated design engineer with diverse work experience since 1979.

• Competent in all aspects of ASIC and FPGA design from initial specification to the final release of the silicon. Experienced in VHDL & Verilog languages, as well as in synthesis, simulations, static timing analysis, and project team leadership. Hard worker, ethical, dependable and effective in both individual and team environments.

• Hold an active US Government Secret Security Clearance.

Technical Summary:

Experienced with these Tool/CAD Systems

• Xilinx FPGA synthesis and timing tools

• Altera FPGA synthesis and timing tools

• Synopsys Synthesis and Timing tools

• Actel FPGA synthesis and timing tools

• Synplicity Synthesis Software

• Modelsim and NcSim simulator

• ClearCase/ClearQuest, CVS, Accurev and SCS .

• Visual Elite for VHDL Design Entry

Experienced with these Languages/Operating systems:

• VHDL & Verilog HDL

• Unix and Windows OS

• Microsoft Word, Excel and Power Point

Familiar with these;

• Perl, Tcl and C languages

• C Shell scripting for synthesis

• NSA Certification process

• High Speed design using SERDES, DDR and PCIe

• SoC, Power PC, NIOS, PCIe and different bus interconnect

• DSP Theories and MATLAB

• Telecom standards such as Sonet, Ethernet 802.3 and ATM.

Special Skills and Knowledge

• Implementation of AES, BATON and MEDLEY Encryption algorithms

• NSA Type-1 Product Suite A & Suite B implementation for HAIPE standard

• Integration of IP cores into user application logic and test bench writing

• All types of PC peripherals such as DMA, UART, and Interrupt Controller etc.

Work Experience:

DRS Technologies – Dayton OH.

7/28/2010 – Present: Senior FPGA Design Engineer.

• Integrated a Digital Down Converter (DDC) core into a main DRS product developed in Merrimack, NH. I used VHDL, Verilog, Modelsim, Xilinx ISE and Matlab to successfully perform my job. The FPGA worked at first try in the lab.

• Created a system level test bench in Verilog to test a large Virtex 6 FPGA. This FPGA included interfaces such as PCie, High speed Xilinx serial and parallel LVDS interface busses along with internal DSP functions.

• Presently I am involved in the integration of PCIe Core from Xilinx and the design of the logic that interfaces with it on the FPGA side. In the implementation of this task, I became very familiar with the PCIe architecture and communication protocol.

L-3 Communication Systems – East Inc. Camden NJ.

6/23/2003 – 6/25/2010: Logic Design Engineer for FPGA and ASIC applications.

• 6/03 – 12/04: Worked with outside consultant on a multi-channel narrowband digital receiver. Responsible for multiple FPGAs. Designed and tested blocks such as High Bandwidth FIR, Sampler, Interpolator, Aliasing, Frequency and Time Domain converters and Fourier Transforms using VHDL. Conducted simulation in Modelsim, synthesis and P&R using Altera software, and verification in the lab. The project was successfully completed and shipped on time to the customer.

• 1/05 – 6/07: Worked on Type 1 HAIPE (High Assurance Internet Protocol Encryptor) products. As team lead, was responsible for the architecture and specification, meetings and status reporting, design, simulation and lab test of three FPGAs. These FPGAs housed encryption codes (such as AES-256, in Galois Counter Mode of operation) and other IPs (such as memory controllers, PLL, Buffers and controls) needed for IP design. Tools employed included VHDL for design, Modelsim for simulation and Altera for Place, Route Timings analysis. The products were successful tested in the lab and shipped on time under the brand names of KG-245A and KG-240A

• 6/07 - 6/08: Architected and specified a Cryptographic Module for a non-type 1 Radio System. This project incorporated an AES Encryption Engine, an embedded processor with multiple and diverse number of peripherals and custom design blocks suitable for a low power, low weight of a radio transmitter and receiver of encrypted stream of data or voice. This customer directed study concluded through a presentation of my FPGA work in a detailed hardware specification.

• 7/08 - 6/09: Designed the DIP-4 Encoder & Checker, Scrambler & Descrambler and Pool Status Calendar described in the Implementation Agreement “OIF-SPI5-01.1” for a high-speed computer security encryptor. Increased understanding of high speed point to point communication and synchronization between FPGAs using LVDS at speed up to 700 Mbps.

• 7/09 to 12/09, Assigned to troubleshoot project in distress. Corrected design errors found in gate-level simulation while the RTL-simulation functioned properly. Assisted in finishing up specifications in order to comply with the Capability Maturity Model Integration (CMMI) process standard.

• 1/10 to 6/10, Architected and designed a HAIPE block to fit and work within the constraints of FPGAs already placed on a board for the Joint Strike Fighter (JSF). The design worked in the lab on the 1st try and management was happy.

Axiowave Networks Inc. Marlboro, MA.

10/07/2001 – 2/08/2003: Logic Designer.

• Specified, architected, designed, verified in simulation, synthesized, and placed & routed, an Egress Packet Processor FPGA. This FPGA was used in the Axiowave Router Line Card and it included IPs such as a POS-PHY4, PCI and a High Speed Coprocessor Interface at 350 MHz DDR, and my own design which included multiple instances of FIFO, DPRAM for table look-up, a Processor interface for Status, control registers and diagnostics and many State Machines to process the data flow and implement the needed function. The tools used were HDL Verilog, VCS Sim, FC2 Synopsys compiler and Xilinx layout tools

• Had the opportunity to learn about the linked-list memory structure in an attempt to map the switch FPGA chip to ASIC implementation.

Coree Networks Inc. Tinton Fall, NJ.

4/23/2001 – 8/24/2001. Logic Designer, Lead Engineer.

• Architected, designed and tested in VHDL a SONET Framer for 2.5Gbps transmitter and receiver logic. The Framer consisted of Scramblers, CRC/ECC and FIFO and interfaced between the core logic and the SERDES. This block was a major part of three ASICs.

• Work included the coordination of the SERDES IP, the analysis of Ethernet vs SONET protocols, the VHDL design, Modelsim simulation and Synopsys synthesis of the block.

PMC-Sierra. Allentown, PA.

2/07/2000 – 4/23/2001. Logic Designer.

• Designed and tested in HDL Verilog a complete receiver for a 3.125 Gbits Ethernet protocol. The receiver consisted of a comma aligner, 8b/10b Decoder, FIFO for frequency compensation and for lanes trunking. The design met the IEEE XAUI Gigabit Ethernet Standard. Design was synthesized to a 320MHz Clock using Synopsys

Lucent Technologies Microelectronics. Allentown, PA.

5/01/95 – 2/04/2000. Logic Designer.

• As a member of different design teams, I was responsible for the architecture, design and verification of functions such as SDRAM memory controller and the video display block for an HDTV video decoder chip. Also responsible for the integration and testing of 10/100Mbits Ethernet transceiver in a SoC ASIC. Work included design in VHDL and Verilog, simulation in Modelsim and presentation using Microsoft Office

IBM, Boca Raton, FL

01/90-04/95: ASIC Lead Design Engineer for multiple PC IO Chipset

12/86-12/88: Project Management for AS/400 I/O adapters

06/83-12/85: PC ISA Adapter Board Design.

01/79-05/83: Manufacturing Test Engineer

Education: MS, Computer Engineering - University Of Miami, 12/78.

BS, Electrical Engineering - University Of Miami, 12/77.

Miscellaneous: Speaks different languages. Enjoy people and work well in a team.

References: Willing to provide a list of references upon request.

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