High School Design

ASHISH SHYAMAL PURANI

***, ***** ******* ***., **** Tunnel Road, Murugeshpalya

Bengaluru, Karnataka 560017, India

Main +918*********

Home +919*********

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Career Objective

To become a responsible part of the organization by optimally utilizing my technical and problem solving abilities.

Professional Profile

STMicroelectronics, Greater Noida, NCR, New Delhi

Intern, 2011 - 2012

• Conducted a study on the cutting edge VLSI technology - FDSOI, to support findings for improvements on current and future technological changes in low power and high performance domain.

• Created a reference manual explaining the concepts of FDSOI and its advantages over conventional CMOS technology.

• Learnt about the basics of IC-Package Co-design (SiP).

• Learnt the tool Virtuoso schematic and layout editor (Cadence) and performed DRC and LVS checks using Calibre tool (Mentor) on the designs in 28 nm and 40 nm technologies.

• Learnt the basics of the tool SoCEncounter (Cadence) to understand the RTL to GDS flow.

DOEACC Centre, Calicut, Kerala

Student, 2008 - 2009

• Implemented and verified an RTL code for ALU module of an 8-bit RISC processor using the tools Modelsim 6.2b SE and Xilinx ISE 9.2i.

Academic Qualifications

M. Tech., VLSI Design, 2012

Nirma Institute of Technology, Ahmedabad, Gujarat

Percentage: 75.7

PG Diploma, VLSI Design, 2009

DOEACC Centre, Calicut, Kerala

Grade: A (75-90%)

B.E., Electronics & Communication, 2007

Govt. Engg. College, Modasa, Gujarat

Percentage: 66.67 (Aggregate)

H.S.C., Science, 2003

Best High School, Ahmedabad, Gujarat

Percentage: 68 (PCMB)

S.S.C., 2001

Best Higher Secondary School, Ahmedabad, Gujarat

Percentage: 86.29

Summary of Skills

Languages

Verilog, VHDL, PERL basics, TCL basics

Operating Systems

UNIX, Linux, Microsoft Windows 7/Vista/XP/2000, MS DOS

Tools

Xilinx ISE, Mentor Graphics tools (Calibre, Modelsim, Eldo Simulator), Cadence tools (Virtuoso Layout & Schematic Editor, ICFB, SoCEncounter), Microwind

Presentations

• "IC-Package Co-design", at STMicroelectronics, Greater Noida.

• "FDSOI Technology", at STMicroelectronics, Greater Noida.

• "Verification Challenges", at Nirma Institute of Technology, Nirma University.

• "Verilog HDL", at Nirma Institute of Technology, Nirma University.

Personal Data

• Marital Status: Single

• Languages Known: English, Hindi, and Gujarati

• Permanent Address: 66, "Ekatra", Vinay-Vihar Hsg. Soc; Baherampura, Ahmedabad, 380022, Gujarat. Additional Information

Secured 91 percentile in GATE 2010.

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