HSIU-WEI (Stanley) CHU
Sunnyvale, CA 94087
=== QUALIFICATIONS ===
Adept professional with VLSI digital & computer system design and multimedia applications seeks a full time position in ASIC design engineer, digital IC design engineer, DSP IC design engineer and Verification engineer. Proficient in both hardware and software design. Works well both individually and as part of team. Fluent in English and Chinese.
Specialized in Verilog and VHDL (RTL) coding design, simulation and modeling. Experienced in Cadence virtuoso, ePD, Magic, Nanosim, NC Verilog, Modelsim , Hspice and Synopsys design analyzer/compiler simulation tools. Knowledge in FPGA, Synthesis, design for test(DFT), function validation or test and mixed-signal.
Knowledge in TI DSP chip, digital image processing and video application. Experienced in C/C++, MATLAB, Visual Studio and Code Compose Studio 3.0.
=== EDUCATION ===
UNIVERSITY OF SOUTHERN CALIFORNIA, Los Angeles, CA
Masters of Science (MS), Electrical Engineering, GPA 3.5(overall), 3.86(VLSI related), Aug 2008
NATIONAL CHUNG CHENG UNIVERSITY, Chia-Yi, Taiwan
Bachelors of Science (BS), Electrical Engineering GPA 3.73, Jun 2003
=== ACADEMIC PROJECTS ===
Tomasulo Processor in VHDL (Aug 2008)
* Conducted the out-of-order CPU in Tomasulo algorithm: the front-end is the instruction fetch Queue and Dispatch unit with RST; the back-end is the issue unit, functional units, Common data bus (CDB), Load store queue.
* Implemented without considering reorder buffer, branch prediction and speculative execution.
Five-Stage Pipeline CPU by Using VHDL and Synthesize by Xilinx ISE (Jul 2008)
* Performed a RSIC 5-stage pipelined CPU with forwarding units and hazard detection units in VHDL and implemented on the Xilinx Spartan 3E FPGA board and confirmed the final data memory or register file contents using the Picoblaze based Hyper Terminal.
* Timing optimization with adding multi-cycle and false paths in timing constraint and identifying the maximum delay path and reducing combinational logic in the path.
Digital System Design (Jun 2008)
* Conducted lab sessions in FIFO (with depth and width expansion), handshaking, memory interface, PCI Bus protocol, CAD tools, Gated Clocking and (non)linear pipelines circuitry design.
Troy 128-bit Wide Word Processor (Apr 2008 - May 2008)
* Built a four stage pipeline CPU with wide word and twenty basic instructions using Verilog and Synopsys Design Compiler.
* Implemented booth multiplier with pipeline structure and supported various bits operation and participations.
HIHO Viterbi Decoder (Mar 2008)
* Designed Viterbi encoder and decoder using Verilog, PrimeTime software and Synopsys Design Compiler to communicate data from a simulated noisy channel and get corrected data streams for performance evaluation.
* Used branch metric unit, adder compare select, path metric state memory and survivor path pipeline, including behavioral RTL implementation, synthesis and post synthesized simulation
Direct Digital Synthesizer (Sin Wave Generation), Team Project (Aug 2007 - Dec 2007)
* DDS generated sinusoidal waveform of a fixed frequency, determined by binary coded input frequency control word.
* Performed a phase accumulator and a high resolution and fast settling time DAC with circuit simulation, device layout, custom chip design techniques, and chip level design.
* Optimized clock frequency, area, power consumption, and performance.
64K and 10K 0.18 Macron SRAM Design, Team Project (Nov 2007)
* Developed and sized a 10K Bit SRAM with 10-bit wide words and 64K Bit SRAM with 16-bit words (schematics in both and layout in 10K).
* Implemented and optimized decoder, sense amplifier, pre-charge circuit and control signal circuit to achieve read and write operation.
28-bit Phase Accumulator with High-Throughput Low Latency Pipelined Tree Adder (Oct 2007)
* Han-Carlson architecture with logical effort performance optimization.
* Assigned a 28-bit unsigned frequency control word as input, which then multiplied itself until output of the adder reached its maximum value and then resets.
Real Time Video Classification in Advance DSP Lab, Using T1 DSP 6713 Chip (Jan 2008 - May 2008)
* Classified different video types by using the features of inter-frame motions and scene change.
* Coded by standard c language considering the limited memory space to achieve real time issue.
Filter Design in Advance DSP Lab, Using T1 DSP 6713 Chip (Feb 2008 - Mar 2008)
* Designed a filter to improve music quality by noise reduction.
Digital Imaging Processing (May 2007 - Aug 2007)
* Noise Removal, Edge Detection, Geometric Modification, Morphological Processing, Texture Analysis, and Optical Character Recognition (OCR).
MPEG Video Layer Based Compression (Jan 2007- May 2007)
* Processed given video frames to find objects in motion or macro blocks.
* Divided each video frame into background and foreground macro blocks, compressed them using various quantization values and DCT coefficients and decompressed and decoded video frames from the input file.
=== WORKING EXPERIENCE ===
Staff Librarian, USC Library, Los Angeles, CA (Apr 2007 - Aug 2008)
* Assisted library patrons with book selection and general technological issues.
Maintainance Engineer, Hsun Tung Computer Inc, Taipei, Taiwan (Mar 2005 - Aug 2006)
* Consulted on technological issues and maintained computers with customers.