Project Design Engineer experence of 0.7yrs

Siddarth Mandalapu +91-809-***-**** Physical Design Engineer ********.*********@*****.***

Career Objective

Seeking to work as a key player in an innovative and competitive environment which provides an opportunity to utilize my skills and realize my potential with total commitment for a responsible position as a physical design engineer in a renowned organization.

Personal Profile

Advanced diploma in ASIC designing at RV-VLSI design center, Bangalore.

Merit level scores, academic excellence certificate in professional engineering studies (73.48%).

Merit level scores in pre-university (91.30%) and High School (81.67%).

An able vocabulary and presentation skills on stages of student technical exhibition events, paper presentations and workshops.

Sports and Social Service.

Education

RV-VLSI design center – Bangalore, Karanataka

Advanced Diploma in ASIC design – 2011-12

Swarna Bharathi Institute of Science and Technology – Khammam, Andhra Pradesh

Bachelor of Technology in Electrical & Electronics Engineering – 2007-11

Spectra Junior College – Khammam, Andhra Pradesh

Board of Intermediate Education – 2005-07

Harvest Public School – Khammam, Andhra Pradesh

Secondary School Certificate – 2004-05

Technical Experience

Extensive knowledge of ASIC flow like RTL-Design, Verification, Timing analysis and Physical design.

Knowledge of design flow methodology for custom flow; Layouts development and verification[DRC/LVS/Parasitic extraction]

Plain knowledge in digital design and CMOS concepts

Experience in designing and developing of standard cell with different drive strengths and OPAMP layouts.

Hardware description language - verilog, VHDL

EDA tools known and worked: Questasim 6.4b (Mentor Graphics), Design Compiler (Synopsys), Quartus (Altera), Prime-Time (Synopsys), layout editor icstudio (Mentor Graphics), ICCompiler (Synopsys).

Project Experience

L.V.S Rule-deck

Objective: To develop the L.V.S rule-deck for the calibre tool using icstudio of Mentor Graphics

Deliverables: Common rule-deck for all the Gates, BJT, Resistors and Capacitors

Tool used: Mentor Graphics: calibre rule writing (LVS)

Team size: six

Brief description:

Project aims at the developing the common rule-decks for all the gate devices and circuit components as resistors and capacitors. Project is done in two levels, first developing rule-decks individually for all the devices and components and in second stage developing a common rule-deck.

Challenges: Finding the Seed Layer for the device recognition

Design of STANDARD CELLS

Objective: To design Standard Cells using 90nm technology

Deliverables: characterized standard cell library

Tool used: icstudio

Brief description:

Project aims at the full custom design layout for the standard cells. The standard cells designed are of different strengthens ranging from 2x to 32x for the universal gates and flops. All the cells are DRC and LVS verified.

Challenges: Finger Technique and Cross-Talk

Digital stopwatch

Objective: Product design of digital stopwatch

Deliverables: Synthesizable code

Tool used: Questasim 6.4b

HDL used: Verilog

Brief description:

Project aims at the coding of the product oriented digital stopwatch in three stages. At first stage only the counter is initiated. In second stage and third stage the design development starts from connecting digital stopwatch to four pins (as such A,B,C,D) whereby providing features like start, stop, resume, pause and ends by proving basic feature that a basic digital stopwatch would have as such alarm and countdown timer. This digital watch runs at a frequency of 50 MHz.

Challenges: connecting concept of HZP generator to pins

Inter IC communication Bus protocol:

Objective: Reverse engineering

Deliverables: code in verilog

Tool used: Questasim 6.4b

Brief description:

Project is basically a reverse engineering of the VHDL code developed for a general two wire protocol, (as such SCL, SDA), which are connected to all the devices on the I2C bus. The total code is reprogrammed to Verilog.

Challenges: understanding the VHDL coding and reprogramming in Verilog

UART

Objective: System Integration

Deliverables: data transmission from transmitter to interface module

HDL used: verilog

Tool used: Questasim 6.4b

Brief Description:

Project aims at the concept of system integration UART module to a Microprocessor. This is done in two stages. In former stage basic receiver and transmitter set functionality is checked. In consecutive stage it is integrated to a microprocessor which completes system integration.

Challenges: Perfect data acquisition from transmitter to receiver module.

Sensor-less control of PMBLDC motor with sliding mode controller

Objective: New sensor-less control technique of PMBLDC, even at low speeds

Brief Description:

Project presents the theory and implementation of a novel sensor less control technique for the brushless dc (BLDC) motor using MATLAB. The proposed new sensor less drive method solves the problem of the sensor less BLDC motor drives at very low speeds. It provides a highly accurate and robust sensor less operation from near zero to high speeds. For this purpose, an approach, a new flux linkage function is defined, that is speed-independent position function with sliding mode controller.

Role:

Project Leader.

Complete Project Planning, Documentation and simulation block designing.

Analysis of reports on the simulation results and Final Project Presentation.

Speed sensor-less separately excited dc motor drive with an adaptive observer

Objective: Usage of adaptive observer for sensor-less DC motor drive which is separately excited

Brief Description:

Electric machines are very important part of our everyday lives, and in that machines which run on DC are considered as the basic EM’s. These are primarily used for power generation and to provide mechanical work in industries. So the project’s aim is to present an adaptive observer to estimate the rotor speed and further the stability analysis of this speed estimation. A modified feed forward control is integrated with the adaptive observer to simplify the above implementation. The design guideline for feedback gain and the speed controller are also given to assure system stability for the entire operating region and simulation results are also obtained to probe it better.

Role:

Project Leader and Team player.

Complete Project Planning, Documentation and Presentations.

Professional Achievements

Paper Presentations at national level tech meets

o Witricity- wireless electricity transmission

o Geothermal energy-the potential power

o Humanization to Dehumanization – ‘CyboFree’

o Snake in next generation of power production

Participation in national level tech fests as such ‘Convergence’ and won merit certificates.

Organizing and participation in inter and intra college tech fests and Workshops.

Personal Details

Father Name : Mandalapu Veeraiah

Mother Name : M.B.Saroja

Age : 22 yrs

Nationality : Indian

Languages : Fluent in English, Telugu and Hindi

Address : 11th Main, HSR Layout, Bangalore, Karnataka, India-560034.

Close note - Work Attitude

I may not possess all the paper qualification and impressive work experience in the world, but what I’ve got is the inherent passion for the job I do and I believe that will sure make a big difference at every challenge thrown at me.

(Siddarth Mandalapu)

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