Design High School

SANTHOSH KUMAR KOTHAKOTA

Email:************@*****.***

Ph no: +917********* _____________________________________________________________________

OBJECTIVE

Challenging career in the field of ASIC Design and keep my personal skills in practice in an organization that provides a professional work atmosphere and ample opportunities.

SUMMARY OF QUALIFICATIONS

Good understanding of the ASIC and FPGA design flow

Experience in writing RTL models in Verilog HDL and

Testbenches in SystemVerilog

Very good knowledge in verification methodologies

Experience in using industry standard EDA tools for the front-end design and

Verification

VLSI DOMAIN SKILLS

HDLs: Verilog and VHDL

HVL: SystemVerilog and PSL

Verification Methodologies: Coverage Driven Verification Assertion Based Verification

TB Methodology: VMM

EDA Tool: Modelsim and ISE

Domain: ASIC/FPGA Design Flow, Digital Design

Methodologies

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage, Synthesis,

PROFESSIONAL QUALIFICATION

Maven Silicon Certified Advanced VLSI Design and Verification course

From Maven Silicon VLSI Design and Training Center, Bangalore, 2012

POST GRADUATION : M.V.G.R College of Engineering,(2009-2011)

M.Tech Specialization:VLSI SYSTEM DESIGN 73%

ENGINEERING : SISTAM College Engg, 63%

(B.Tech) E.C.E Srikakulam(2005-2009)

PRE-UNIVERSITY : M.P.C, Sri chaitanya Jr College, 84%

Visakhapatnam(2003-2005)

SCHOOL(SSC) : Abhyudaya convent and high School, 88%

Bobbili(2002-2003)

ACHIEVEMENTS

Presented a paper in a National Conference ‘DEVICE2010’, titled “A low power high speed hybrid Cmos full adder in nano scale” in ANITS College of Engineering.

Presented poster on Wireless Robo Crane at GITAM University.

Attended a NATIONAL LEVEL WORKSHOP ON CADENCE TOOLS organized by GITAM UNIVERSITY.

Attended a NATIONAL LEVEL WORKSHOP ON XILINX TOOLS organized by GMRIT.

EXPERIENCE

November 4th 2011 – March 4th 2012, Maven Silicon,

VLSI Design and Training Center, Bangalore

VLSI PROJECTS

M.Tech Project Title: Design and Implementation of Variable Field Programmable CRC Circuit Architecture.

HDL: VHDL

EDA Tools: Modelsim and ISE simulator

Description: The design and implementation of a variable field programmable cyclic redundancy check (CRC) circuit architecture, suitable for deployment in network related and packet processing, security processing and storage related functions is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The architecture is supports the input data width 32 bits, 64 bits, 128 bits, 256 bits also and variable polynomials also.

Title 2: Router 1x3 – RTL design and Verification

HDL: Verilog

HVL: System Verilog

EDA Tools: Modelsim, Questa -- Verification Platform and ISE

Description: The router accepts data packets on a single 8-bit port called data and routes the packets to one of the three output channels, channel0, channel1 and channel2.

Architected the design and described the functionality using Verilog HDL.

Architected the class based verification environment using system Verilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

PERSONAL PROFILE

• Father’s Name: Sri K Venkata Ramana

• Mother’s Name: Smt. K Varalakshmi

• Permanent Address: Palagara village, Balijipeta mandlam,

Vizianagaram district, Andhra Pradesh. Pin: 535557.

• Contact no: +91-741*******

• Date of Birth: 21st June, 1988

• Marital Status: Single.

• Nationality: Indian.

• Languages Known: English, Hindi, and Telugu.

• Hobbies & Interests: Cooking, Listening Music.

Declaration

I hereby declare that all information given by me above are true and correct to the best of my knowledge.

Date:

Place: Bangalore Santhosh kumar kothakota

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