M.tech (VLSI DESIGN) ADDRESS: ***, ROYAL MANOR
NIRMA UNIVERSITY HAL III STAGE,
E-MAIL: firstname.lastname@example.org KODIHALLI,
MOBILE NO: +918********* BANGALORE-56008
2 years of professional experience in Analog Circuit Design and Verification.
1. Terminus Circuits Pvt. Ltd, Bangalore as Circuit Design Engineer (1st July 2011-Till Date)
Responsible for CMOS Transistor Level Circuit Design and Verification of High Speed IP Blocks.
i. Work with Analog/Digital circuit block and integrate the various IP block.
Working as a circuit Design Engineer in USB 3.0 Design Team
Design and characterization of Phase Locked Loop (PLL) in TSMC 90nm process.
2.5GHz Charge Pump PLL.
Hands on Design Experience of Digital Loop Filter (DLF) of Receiver circuit.
High Speed I/O design, LVDS and SSTL.
Verification (Verilog) of Digital Loop Filter (DLF).
AMS Verification of Receiver circuit of USB 3.0( VGA, FFE, DFE,) using Verilog-A.
Efficient utilization of cadence tools.
Good basics of Analog CMOS Circuit Design, Device Physics, MOSFET Device Models.
Working on CADENCE IC station 6.1.4 (Virtuoso, Schematic Editor, Analog Design Environment, Spectre,Virtuoso Layout Editor and Assura).
2. Central Electronics Engineering Research Institute(CEERI), Pilani (12th July 2010 – 30th April 2011)
Designed Flash ADC and Asynchronous Binary search ADC for UWB Application in 180nm process.
Sub Blocks of Flash ADC like Resistor string DAC, Latched Comparator, TC to BC Encoder circuit etc.
i. Worked on project title “Analysis and Design of Analog to Digital Converter (ADC) for Ultra Wide Band (UWB) Application" sponsored project from C-DOT under GAP.
ii. Designed two ADC architectures for UWB application and compare power consumption and total conversion time for both ADCs and find best suitable architecture for UWB application.
Worked in IC Design Group (IDG) as VLSI design Trainee.
Worked with Analog & Mixed signal (AMS) Design Team as a part of CMOS circuit Designer.
i. Designed Data Converter Circuits.
ii. Worked on UMC 180nm technology.
worked with Cadence tool – Schematic composer-Spectre and Layout Design-Virtuoso
Exercised Analog Macro’s Design from specification to final GDS.
EDA Tools: CADENCE IC Station 6.1.4, Spectre schematic composer, Virtuoso, NcSim, AMS simulator Ultrasim, Tanner, Mentor Graphics, Microwind (layout design tool)
Hardware descriptive language: VHDL, Verilog
Programming Tools: Xilinx ISE simulator, Matlab R2010, Modelsim 6.3, Altera Quartus 7.2
Operating System: Windows XP, Linux, Windows 7
• M.tech (VLSI Design) from Nirma University with CPGA of 7.41/10.
• B.E (Electronics & Communication) from North Gujarat University with aggregate of 65%.
Title: Analysis and Design of Flash Analog to Digital Converter for Ultra Wide Application at NUiCONE International Conference at Nirma University and that got published in IEEE xplorer Digital Library.
EXTRA CURRICULAR ACTIVITIES:
• Got third Prize for MODEL PRESENTATION in State level Technigma.
• Participated in “State level Vie-fi” competition in ROBOTICS.
• Participated in Workshop on “Low Power VLSI Design” held at Nirma University.
AREAS OF INTEREST:
• Analog and Mixed Signal Design
• High Speed-Low Power Design
Full Name: Piyush Kanodiya
Address: 7/Abhinav society, Somnath road, Mehsana-384001,Gujarat.
Date of Birth: 22/05/1987
Marital Status: Single
Language Known: English, Hindi, Gujarati
(1) Dr. N. M. Devashrayee (2) Dr. S. C. Bose
PG coordinator, M.tech (VLSI Design) Scientist ‘F’
Nirma Institute of Technology, IC Design Group,
Nirma University, CEERI, Pilani
Ahmedabad-382 481 Rajasthan
M- 098******** E-mail:email@example.com
I hereby assure that all the data given above are true to best of my knowledge. I look forward to hearing from you.
Place: Bangalore Name: Piyush Kanodiya