SAI SUHAS ARRA

+1-317-***-****, adjbei@r.postjobfree.com 2991 Stadium Dr,

linkedin.com/in/sai-suhas-arra-i1997 Columbus, OH. Summary:

Actively looking for Full time Positions in ASIC/RTL/SoC Design, Verification. Education:

● Ohio State University GPA:3.5

MS in Electrical and Computer Engineering

Coursework: Computer Architecture (Advanced), Computer Architecture and Design, HDL Design and Verification, Mixed Signal VLSI, Advanced Microcomputers, Machine Learning, Project Management

● University College of Engineering, Osmania University, India GPA:3.78 Bachelor of Engineering in Electrical Engineering

Skills:

● Programming/Hardware Languages: C++, C, Python, System Verilog, Verilog, VHDL, Embedded C, Assembly Language

● Verification Methodology: UVM

● Tools: QuestaSim, Cadence Virtuoso, Xilinx Vivado, ModelSim, Synopsys VCS, Keil μ Vision, Matlab Achievements:

Google India Challenge Scholarship Pytorch (Facebook) Scholarship Experience:

Autonomous Mobility Intern LHP Engineering Solutions, USA

● Extensively worked on Zed Camera and Jetson TX2. Developed Python scripts to estimate the real-time distance of the leading vehicle with high accuracy up to 2.5m.

● Modified C++ code of the Brake ECU to integrate the Brake by Wire module to the existing autonomous vehicle design.

Embedded System Design Intern Centre for Development of Advanced Computing, India

● Gained Important insights into ARM microcontroller, Architectures, Memory, Embedded C Programming.

● Experience with UART, SPI, I2C protocols, WDTs etc by performing several simulation projects on ARM Cortex-M3 Microcontroller.

Training:

Mentor Graphics (Siemens):

o System Verilog – Fundamentals, OOP and IPC, Randomization and Functional Coverage o UVM

o QuestaSim

Academics:

● Custom Design of Synapse for a Cognitive Image Sensor Cadence Virtuoso 45nm pdk o Designed schematic and layout of memory unit which includes design of SRAM for storing synaptic weights, row and column decoders, write drive circuit, precharge and sense amplifier circuits. o Implemented Brent Kung architecture for adder design in the classifier circuit. o DRC, LVS, Post layout parasitic extraction was performed and also optimized the circuits to reduce the delay.

o Achieved a highly accurate system with a clock speed of 3.9 Ghz.

● Implementation and Verification of DDR3 Memory Controller System Verilog, Modelsim o The memory model was leveraged from Micron. Designed the Memory controller through a state machine structure as per Micron data sheet specifications and then connected to a predefined DDR3 Memory. The testbench has been created using verification environment and class-based implementation.

● Dynamic Branch Predictor C++

o Implemented a Branch Predictor with Perceptrons using C++. o Simulated using 10 short traces (~30 million instructions) derived from CBP-1 and 10 long traces (~150 million instructions) and obtained an average misprediction rate of 3.78.

● Design and verification of a 5-stage pipelined MIPS Processor Verilog, UVM, QuestaSim o Designed a 5-stage pipelined MIPS Processor in Verilog. The functionality of instructions is tested using Constrained Random Verification and data dependencies handled by the hazard unit are verified by Assertion based Verification.

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