BALLA SIREESHA

Address: Challapalli, Pin:****** Email:adj430@r.postjobfree.com

Contact No: +91-767******* LinkedIn:adj430@r.postjobfree.com OBJECTIVE

To enhance career development and gain knowledge within VLSI industry by accepting and executing challenging duties continuously by learning new skills, and utilizing my knowledge and communication skills towards organization goals.

EDUCATION

S.No Course Name of the Name of the Year of Percentage Institute Board/University Completion

1 B. Tech. (Electronics Gudlavalleru Jawaharlal Nehru 2018 8.5 CGPA and Communication) Engineering technological

College, University,

Gudlavalleru Kakinada

2 Intermediate Vijaya Junior Board of 2014 95.5

College,

Challapalli

Intermediate

Education

3 S.S.C Vidyodaya Public State Board of 2012 9.7GPA School,Challapalli Secondary

Education

PROFESSIONALTRAINING

ADVANCED VLSI DESIGN AND VERIFICATION COURSE - Maven Silicon VLSI Design and Training -23 Jan 19 – Till the date.

Perform RTL coding.

Designing and developing RTL code using VHDL or Verilog .

Good at FPGA front end design RTL coding techniques.

Good at writing Test benches using System Verilog and UVM

Very good knowledge in verification methodologies. SKILLS

VLSI Domain Skills

HDL : Verilog

HVL : System Verilog

Verification

Methodology

: Coverage Driven Verification, Assertion based Verification TB Methodology : UVM

EDA Tools : ISE – Xilinx, Riviera Pro – Aldec, Linux Commands Domain : ASIC/FPGA Front-end Design andVerification Knowledge : RTL Coding, FSM based Design, Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis, ABV-SVA Technical Skills

Programming

Languages

: C – Language, basics of Perl

Knowledge on : Digital Electronics

CURRICULUM PROJECT

ROUTER 1 X3 – RTL DESIGN AND VERIFICATION- Maven Silicon VLSI Design and Training HDL : Verilog

HVL : System Verilog

TB

Methodology

: UVM

EDA Tools : Xilinx - ISE, Riviera Pro – Aldec

Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2. Responsibilities:

Architected the block level structure for thedesign

Implemented RTL using Verilog HDL.

Verified the RTL model using System Verilog.

Generated functional and codecoverage.

Synthesized the design.

ACADEMIC PROJECT

SPI CONTROLLER CORE – DESIGN AND VERIFICATION

HDL : Verilog

HVL : System Verilog

TB Methodology : UVM

EDA

Tools

: Xilinx – ISE, Riviera Pro – Aldec

Description: The SPI IP core provides serial communication capabilities with external device of variable length of transfer word. This core can be configured to connect with 8 slaves. Responsibilities:

Architected the block level structure for the designspecification.

Implemented RTL using Verilog HDL.

Architected the class based verification environment in UVM.

Defined Verification Plan.

Verified the RTL module using System Verilog.

Generated functional and code coverage for the RTLverification. STRENGTHS

Quick Learner.

Being an enthusiastic person to learn the newthings.

Analytical Thinking.

PERSONAL DETAILS

Father Balla Sambasiva Rao

Mother Balla Kanaka Durga

Gender Female

Date of Birth 16-04-1996

Blood Group O +ve

Languages Known English, Telugu

Declaration:

I hereby declare that information furnished above is true to the best of my knowledge. Place: Vijayawada Signature

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