Engineering Sec School

CAREER OBJECTIVE:

“To deliver my duties to the fullest satisfaction of the superiors and subordinates and for each responsible position in future, work for the betterment of the company in any circumstances.”

WORKING EXPERIENCE:

I had 1 year and 3 month working experience in Madurai Institute of Engineering and Technology as Assistant Professor.

EDUCATIONAL QUALIFICATION:

Completed SOC Verification course as a intern for 6 month in SION SEMICONDUCTORS Private lmt (Bangalore).

M.E in VLSI Design (2019) from Kalasalingam Institute Of Technology- Sriviliputhur with 8.5 CGPA.

B.E in Electronics & Communication Engineering (2017) from Sethu Institute Of Technology- Viruthunagar with 8.863 CGPA with I class Distinction.

12th Standard (2013) from Holy Family Girls Hr.Sec School-Madurai with 87.3%.

10th Standard (2011) from Holy Family Girls Hr.sec School-Madurai with 95.8%.

TECHNICAL SKILLS:

Programming Languages: C, Verilog, System Verilog

Operating Systems : Windows XP,7,8, MAC

Application packages : MS OFFICE, MATLAB,XILINX ISE,MODEL SIM

AREAS OF INTEREST

Digital Electronics, VLSI Design.

CONFERENCES:

•Participated in International conference,entitled “Interface SRAM with APB Protocol using system verilog” in PET Engineering college(2019).

•Participated in International conference, entitled“Design and Implementation of APB3 Protocol” in Kalasalingam institute of technology (2019).

•Participated in International conference,entitled “A 3D die stack method for self repairing process” in PET Engineering college(2018).

•Participated in National conference,entitled “A 3D die stack method for self -repairing process” in Theni kammavar sangam college of technology,Theni (2017).

CURRICULAR ACTIVITIES

Workshop:

Participated in “Sanus’15” Workshop entitled “RASPBERRY PI” held at SNS College of engineering Coimbatore.

Participated in “NATIONAL WORKSHOP” entitled “Recent advancement in

Embedded Systems with IoT” held on (BIT) Campus Anna University, Trichirappalli

In-plant training:

Attend In plant Training in “RAIL NET SOFTWARE SOLUTIONS”.

ACADEMIC PROJECT:

IN B.E

Title: A 3D DIE STACK METHOD FOR SELF-REPAIRING PROCESS

Domain: VLSI Design

IN M.E

Title: Interface SRAM with APB Protocol using system Verilog

Domain: VLSI Design

KEY STRENGTH

•Ability to learn and grasp new concepts very quickly.

•Organizing Skills, teamwork and ability to adjust oneself in any kind of

environment and Socialize with all peoples.

•Focused and committed towards work and responsibilities.

PERSONAL DETAILS:

Father’s Name : Mr. S.Francis

Mother’s Name : Mrs. F.Thayammal

Date of Birth : 20-10-1995

Gender : Female Marital

Status : Single

Nationality : Indian

Languages known : English, Tamil

Hobbies : Listening Music, Playing Chess, Browsing

Internet

Declaration

I hereby declare that the above details are true to the best of my knowledge.

PLACE : Madurai JEYA BRINDHA DATE :

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