Design Engineering

Name: SABHAVAT ANITHA

E-mail id: ****************@*****.***

Contact No: +91-720*******

Address: *-*-****/** *************, Kachiguda Hyderabad Telangana 500027

Date of birth:07-04-1992 Nationality: Indian

Career Objective: Looking for a responsible position in VLSI domain where contribute myself to the project/organization and enhance my skills and experience towards professional growth.

Work Experience:

Worked for the R & D project received from RCI, DRDO titled “Design and Develop RadHard Standard Cells to Mitigate Effects of SEE and Charge Sharing with SER Estimation for 180nm CMOS Technology”.

Successfully completed 6 months training in Physical Design course with hands-on tools (GENUS and INNOVUS) experience at SYNSOC Technologies Pvt Limited, Hyderabad. During my training, I successfully completed 2 projects (1. Leon processor, 2. ASIC Entity)

Technical Skills and Tool Knowledge:

EDA Tools: Cadence Front End( .V to GDSII) (NC Verilog, NC Launch, Genus, Innovus)

Cadence back end (VIRTUOSO Schematic, Layout editors and physical verification (DRC, LVS),Parasitic Extraction, Post layout simulation using SPECTRE)

Standard cell characterization (Liberate of Cadence)

Physical Verification Tools: Calibre (Mentor Graphics), Assura and PVS (Cadence)

PDKs : SCL 180nm, Cadence GPDKs (180nm, 90nm, 45nm)

Programming Languages: C, VERILOG and SIPCE

Scripting : Perl and TCL.

Operating Systems: WINDOWS and LINUX.

Educational Details

S No.

Name of the Course

Name of the

Board/University

Subjects /Specialization

%

1

M. Tech

(2014-2016)

Sreenidhi Institute of Science & Technology (an Autonomous institute under JNTUH)

Digital Systems and Computer Electronics

85.3

2

B. Tech

(2010-2014)

Jawaharlal Nehru Technological University, Hyderabad

Electronics & Communication Engineering

75.6

3

Intermediate

(2008-2010)

State Board of Intermediate

Andhra Pradesh

MPC

85.1

4

SSC

(2008)

Board of Secondary Education,

Andhra Pradesh

70

Project Details

Project1:

Title: ASIC Entity

Description:Design consist of 29macros and 18k gate count in 45nm technology with 250MHZ frequency.

Entire PnR flow is performed for design to avoid congestion and fix timing violations.

Project2:

Title: Leon processor

Description: Design consist of 4 macros and 35k gate count, entire physical design flow is performed

in 45nm technology. Timing analysis and Sanity checks are performed.

Research Interests:

Low power CMOS VLSI designs

RadHardStandard Cell Library characterizations

Analog and Mixed signal Designs

Designing Secure block for Hardware and Fault tolerant systems

Workshops attended:

1.Five Day workshop on “Hands on training on VLSI Design using CADENCE Tools” organized by Sreenidhi Institute of Science and Technology Hyderabad in collaboration Entuple Technologies Pvt. Ltd, Bangalore.

2.One-week workshop on “Integrated Circuit and system design using CAD Tools” organized by VNR VignanaJyothi Institute of Engineering & Technology in collaboration with Nano Chip Solutions, Bangalore.

3.Two days’ workshop on “MENTOR GRAPHICS HEP-1 TOOLS (BACK END DESIGN)” organised by Sreenidhi Institute of Science and Technology, Hyderabad in collaboration with CoreEL Technologies (I) Pvt. Ltd, Bangalore.

Key Strengths:

Dedicated towards the assigned works with positive attitude.

Prefer to work with team as well as individual.

Good leadership qualities

Ability to learn new technologies with strong determination.

I do hereby declare that all the information given above is true to the best of my knowledge and belief.

Date:

Place:

S. ANITHA

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