Engineer Design

Name: Indukuri Sanyasi Uday Varma

Email Id: ************@*****.***

Mobile: +91-850*******

LinkedIn: https://www.linkedin.com/in/i-s-uday-varma-97819b160/ I am an efficient electronics engineer having hands on skills of VLSI design and verification, who is looking for a great opportunity to implement my learning till now for the welfare of the organization as well as my growth both personally and professionally. Advanced VLSI Design and Verification Course

Maven Silicon, VLSI Design and Training Centre, Bengaluru August 2019-till date.

Educational Qualifications:

Title

Specialization

School/college

Board/

University

Year of

Passing

Aggregate

B.Tech

Electronics and

Communication

Engineering

GITAM institute of

technology,

Visakhapatnam.

GITAM University

2019

6.48

Intermediat

e

M.P.C

Narayana junior

college, Vijayawada

Board of

Intermediate

Andhra Pradesh

2015

94.6

School

C.B.S.E

Kendriya

Vidyalaya no-2,

svn,Visakhapatn

am.

C.B.S.E

2013

9.0

Academic Highlights:

Qualified in GATE 2019.

Internship Experience:

Research Intern Hyderabad, India

Bharath Electronics Limited (BEL) May 2018 30 Days

• Description: In this project I have learnt about the implementation of supply supervision using 18f8620 microcontroller.

Rashtriya Ispat Nigam Limited, Visakhapatnam, India RINL, Steel Plant May 2017 15 days

• Description: In this internship I had completed the in-plant training for 15 days. Career Objective:

Certified Training:

VLSI Domain Skills:

HDL : Verilog

HVL : System Verilog

TB Methodology : UVM

Verification Methodology : Coverage Driven Verification, Assertion Based Verification Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis, DFT, CMOS,FPGA,Digital Electronics.

IT Domain skills : Basics of C, Perl

1.UART IP Core Verification

HVL : System Verilog

TB Methodology : UVM

Description: The UART IP core provides serial communication capabilities, which allows communication with modem or other external devices. UART will operate in three nodes-Simplex mode, Full duplex mode and Loopback mode.

Responsibilities:

• Architected the class-based verification environment in UVM

• Defined verification plan

• Verified the RTL module using System Verilog

• Generated functional and code coverage for the RTL verification sign off 2.Router 1x3-RTL design and Verification

HDL : Verilog

HVL : System Verilog

EDA Tools: Questasim and ISE

Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel 0, channel 1, channel 2.

Responsibilities:

• Architected the block level structure for the design

• Implemented RTL using Verilog HDL

• Architected the class based verification environment using System Verilog

• Verified the RTL model using System Verilog

• Generated functional and code coverage for the RTL verification sign-off

• Synthesized the design

Study and calibration of virtual source model for short geometry MOSFETs Description: In this project we have done construction and implementation of physical model and I- V characteristics and C-V characteristics of short geometry MOSFET having length 32nm and 65nm using TCAD software, NANOHUB virtual source model and compared their results and also fabricated the physical model of finfet which is the tri gate transistor. Curriculum Projects:

Academic Projects:

• Rendered services as Vice Secretary of ECO Visakhapatnam.

• Mentor at SNIST ECO Student Chapter.

• Received third runner-up in state level ABACUS competition twice and third runner-up in

National level ABACUS competition once.

• Participated in the third

World Congress on Disaster Management at Visakhapatnam.

• Attended a workshop on Robo Expedition, IIT MUMBAI.

• Participated in regional level badminton competition twice.

• Ability to work in a team.

• Interactive,self-confidence.

• Playing cricket, badminton.

• Watching movies

Personal Profile:

Date of Birth : 04-04-1998

Father’s name : I.S.V. Madhu Varma

Mother’s name : I. Vijaya Sree

Languages Known : Telugu, Hindi and English.

Declaration:

I hereby declare that the above mentioned information is correct upto my knowledge and I bear responsibility for the correctness of the above mentioned particulars. Date:

Place: Bangalore I.S. Uday Varma

Achievements:

Personal Skills:

Hobbies:

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