SINDHU JANJIRALA
Email :******.*****@*****.***
Career Objective: To get an opportunity to utilize the knowledge and technical skills that I aspire to contribute towards the growth of the company and constantly develop my own set of technical skills over time. I aspire to be technically minded & able to demonstrate numerical and scientific ability and have problem-solving skills.
Academic Qualifications:
Course Institute/Board Year of pass Percentage/ CGPA
B.Tech - ECE CVR College of Engineering
JNTU, Hyderabad 2020(pursuing) 9.4CGPA
Intermediate Sri Chaitanya Junior Kalasala
Board of Intermediate Education 2016 94%
Class X Durga bhavani high school 2014 9.7 CGPA
Technical Qualifications:
• Software Languages : C, Basics of JAVA.
• Hardware Languages : Verilog .
Project 1: CONTROL PATH DESIGN FOR VENDING MACHINE USING VERILOG HDL
The aim of the project is to implement software design and simulation of FPGA based vending machine using Verilog HDL and Xilinx ISE simulator. Here we are using FPGA because FPGA based machines give faster response and uses less power than microcontroller or arduino or ASIC based machines. The utilization performance and timing reports are taken and the design is verified on FPGA Spartan 3E board.
Project 2: IMPLEMENTATION OF REAL TIME DIGITAL CLOCK USING ARDUINO UNO AND GPS RECEIVER
An Arduino based embedded real-time digital clock is designed and implemented using GPS module, Arduino UNO board integrated with an ISM band and seven segment displays. GPS provides continuous positioning and accurate timing information. The GPS module receives highly accurate date and time from satellites with high accuracy atomic clock, are then transmitted to master clock . Two other slave clocks are included to display the date and time in different clocks being use in a same location. The slave clocks receive data through ISM tranciever and driver circuits.
Soft skills:
• I am a honest, self -motivated,Hard working girl with positive attitude towards my career and my life.
Achievements:
• Participated in the paper presentation for CIENCIA 2019 held at CVR COLLEGE OF ENGINEERING.