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Design Operator

Location:
Ernakulam, Kerala, India
Posted:
November 06, 2019

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Resume:

RESUME

ATHULYA S. PAI

Meprathumalil (H),PRRA**A,Vichattu Lane, Near K.S.E.B Perumbavoor,Kerala. Mob: +91-859******* e-mail: adarrr@r.postjobfree.com

Objective

To work with maximum potential in a challenging and dynamic environment, with an opportunity of working with diverse group of people and enhancing my professional skills with learning and experience for career growth.

Technical Skills

Hardware Languages

Verilog,VHDL, Embedded C(Micro-controllers viz. 8051,,PIC16F876A,Atmega 162v)

Software Languages

C

OS

Windows, Linux

EDA Tools

Cadence SOC Encounter, Cadence Virtuoso, Cadence Assura, RTL compiler, ModelSim, Xilinx ISE, Atmel Studio

Educational Qualifications

Degree/ Exam

Subject

Institution

University/Board

Year

Score

Diploma

VLSI Back-end Designing

Indian Institute of VLSI Design(IIVDT), Bangalore

IIVDT

2016

B. Tech.

ECE

Mangalam College of Engineering, Ettumannor

M.G. University

2015

77.00%

Intermediate

Bio-Maths

S.N.H.S.S, Okkal

Board of Higher Secondary Education, Kerala

2011

92.00%

SSLC

St.Joseph’s Girls High School, Chengal, Kalady

Board of Secondary Education, Kerala

2009

90.00%

Professional Experience

Presently working as an Operator in 110KV Substation Malayattoor from 1st November 2016(KSEB on contract basis).

Job Profile

Preparation of Permit Works

Issuing Isolation Certificate for Feeders

Maintenance of Transformers, Feeders, Batteries and Relay Panels.

Routine maintenance of Registers and Yard Equipments.

Certification

I have done a Cadence certified Diploma course in VLSI Physical Design at Indian Institute of VLSI Design(IIVDT), Bangalore.

Projects

1. Physical Design and verification of DTMF chip.

Tool Used : Cadence SOC encounter

Description : Floor planning, power planning, routing, CTS, Design sign off and GDSII of the DTMF chip was done. Technology – TSMC 0.18 microns, Layers- 6, Macros – 4, standard cells – 6k, Frequency – 125MHz.

2. Synthesis of RAM and ROM Blocks

Tool Used : RTL Compiler

Description : Performed Synthesis for RISC Architecture using low power synthesis technique.

Academic Projects

Main Project:

FPGA BASED AUTOMATIC RAILWAY LEVEL CROSS MANAGEMENT SYSTEM

oTo control unmanned railway gate automatically using FPGA platform. Since FPGAs are reconfigurable and it is having high speed than microcontrollers, it is best suitable for controlling railway gate by reducing the errors caused by manual operation. Xilinx Spartan 3E is used in this project.

Mini Project:

AUTOMATED SHOPPING MEGA CART

oThis automated shopping mega cart is a sensible mobile grocery aid which supports customers in shopping process. It is designed to speed up the process of purchasing and avoids large queues in front of cash counters. PIC microcontroller is used in this project.

Personal Information

Date of Birth

20-04-1994

Gender

Female

Indian Languages known

English,Konkani, Malayalam

Hobbies & Interests

Reading, Music

I hereby declare that the above information is true to the best of my knowledge.

Perumbavoor Athulya S. Pai

24-10-2019



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