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Designer Training

San Jose, CA
November 04, 2019

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Kevin M. Bowron

San Jose, CA



An accomplished, driven, and dedicated technical professional with several years of layout industry experience working with multiple departments. A leader skilled at developing teams and leading projects in a global environment. Strengths include working with latest technologies and tools. In addition, a solid knowledge of quality layout design practices.

Commitment to deadlines and project goals

Experience working with global sites

Effective and strong communicator

Problem solving skills

Experience doing custom and standard cell

layout on digital and analog designs

Project Leadership experience

Establish strong relationships with outside departments

Computer Skills:

UNIX, Linux, Windows XP OS, MS Office Suite, Share Point, Cadence Virtuoso tool and Virtuoso XL for IC layout, Virtuoso Custom Router (VCR), Hercules, Caliber


Qualcomm, San Jose Sr. RF Analog Layout Designer (Contract) Jan 2018-Present

Assigned to complete custom RF Analog layout in 14nm, 40nm, and .18um SOI process for TSMC and Global Foundries processes.

Layout work includes LNA, Mixers, BIAS circuits, Level Shifters, and high-level integration.

Applied latest shielding, guard-ring protections, and CLK routing techniques.

Familiar with the latest Cadence Virtuoso Environment.

Infinera Corp., Sunnyvale CA Sr. Analog Layout Designer Nov 2016-Jan 2018

Assigned to complete cell layout, floor-planning, and tape-out verification on 80 GHz DAC in 16 nm Fin-Fet process from TSMC.

Work in 7nm TSMC process on a 130 GHz ADC block.

Worked on Analog cells such as comparators, serializers, Current Mirrors, and DFF for optimum layout.

The layout required completing analog/mix-signal Designs using custom layout techniques, standard cell layout, Infinera Custom standard cell, and interface plan to PnR modules.

Applied latest shielding, guard-ring protections, and CLK routing techniques.

Also required to work with off-site resources in Bangalore India and Canada.

Familiar with the latest Cadence Virtuoso Environment.

Inphi Corp., Santa Clara CA Analog Layout Designer (Contract Position) June 2016-Oct 2016

Sr. Analog Layout Designer

Assigned to complete High Speed CLK Design on PAM project using TSMC 16nm Fin-Fet process. Sub-cells included Voltage regulators, Code Gen, Code map circuit, and CLK generator and required to interface with line-RX PLL.

The layout required doing some analog and mix-signal techniques using custom, standard cell layout, and interfacing to PnR sub-cell.

Floor-planning, extensive shielding and node matching required for design.

Also required to work with off-site resources in Singapore and Vancouver.


Qualcomm, Raleigh NC Layout Designer Contract April 2014 – Dec 2015

Sr. Layout Designer

Working closely with Design team to develop compact high-speed digital layout.

Completed assignments involving layout of Macro’s using mix signal layout techniques on latest process nodes.

Performed integration of Macro’s from development stage to release, includes timing optimization of high speed designs in 10nm and 14nm.

Altera Corp, CA Principal Layout Designer/Sr. Layout Designer 1997-Oct 2013

Principal Layout Designer

A goal orientated Member of Technical Staff layout designer and “Hands-on” Layout group lead of layout designers.

Participated in new product development. Layout lead of Micro Floor Planning group and member of Micro floor Planning group.

Coordinated test chip development, process impact studies, and flag ship development.

Worked closely with global layout teams to set methodology for layout group. This group focus was handling issues with metal migration, metal density, Antenna, Latch-up, LOD, WPE, signal integrity, and productivity.

Completed assignments involving layout IP development of some analog and mostly mix signal custom layout on latest process nodes.

Performed integration of a billion transistor gate designs from development stage to tape-out, including floor planning, power planning, and timing optimization of high-speed designs in 0.35, 0.25, 0.18, 0.13, 0.11, 90nm, 40nm, 28nm and 20nm technologies.

Design Layout Supervisor

Flagship Project lead assigned to coordinate work assignments, complete full chip assembly and verification. Projects included the APEX, Stratix I, II, III products.

Performed integration of over a billion transistor designs which included power planning and timing optimization of high-speed design.

Process development for die size and layout impact.

Developed the layout training on Cadence custom router for layout group.

Sr. Layout Designer

IP block leader for memory development of 10K and Mercury projects.

Assignments included full range of layout development, this involved working closely with design on CRAM, Memory Arrays, Routing Fabrics, Data/Address Register, LUT, PLL, I/O, and Power management development.

Additional Relevant Experience

Telcom Semiconductor, CA Sr. Layout Designer

Selected to complete layout of Digital/Analog devices for power management (DC/AC converters and band Gaps).

Axil Computers, Inc., CA Sr. PCB Layout Designer

AST/GRiD Computers, CA Supervisor of CAD/Layout group

ICI Array Technologies, CA Sr. PCB Layout Designer

Richmar Associates, CA Sr. Electronic Draftsman/Layout Designer

Management Tools:

MS Project Scheduling, Excel Spread Sheets, and MS Power Point Presentation


San Jose City College – Associate of Arts Degree: Drafting Technology

-Certificate in PCB Design and CMOS Layout Technology

Institute for Business and Technology (IBT) – CMOS Layout Design Degree

Specialized Training:

Legal Overview Involved in Managing People

Altera Front Line Leadership

Crucial Discussion Training

Conflict Management Training

Leading through Coaching Training

Preparing Technical Presentations

Motivating and Influencing Training

Managing Stress Training

Interviewing Skills Training

Strengthening Innovation Training

Identifying Priorities and Setting Verifiable Goaloals Training

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