M-Tech in VLSI Design

MOHIT DHIRUBHAI LIMBASIYA

E-mail : ****************@*****.*** Contact Details : 962*******

EDUCATIONAL QUALIFICATION:

Course

Name

Branch School/College Name Board/University

Name

Duration % Marks

/ CGPA

M-Tech VLSI Design Amrita School of

Engineering

Bangalore

Amrita Vishwa

Vidhyapeetham

(Amrita University)

2017-2019 66.50%

B.E Electronics and

Communication

V.V.P Engineering

College, Rajkot

Gujarat Technological

University(GTU)

2012-2016 8.12

(CGPA)

12

th

- Shree Krishna Higher

Secondary School,

Rajkot

Gujarat Secondary &

Higher Secondary

Education Board,

Gandhinagar

2011-2012 57.23%

10

th

- Shree Krishna Higher

Secondary School,

Rajkot

Gujarat Secondary &

Higher Secondary

Education Board,

Gandhinagar

2009-2010 79.69%

COMPUTER SKILLS:

- Cadence : Virtuoso, DRC, LVS

- Mentor Tools: Tanner AMS tool, Questasim, Modelsim, layout using Pyxis, DRC and LVS using Calibre

- Xilinx: Vivado Design Suite

- VLSI Design Layout Tools: Cadence, Mentor Graphics, Microwind

- Programming Skill: C, verilog.

- Operating System known: Windows, Linux

- Electronics Circuit Simulation Tools: PSpice, LTspice

- Microsoft Office

ACADEMIC PROJECT’S:

Cadence Virtuoso:

- I implemented digital circuits in the subthreshold region. Here I also analyze the effect of temperature, supply voltage and device sizing in different process corner using monte-carlo simulation.

- I implemented 12T SRAM cell and compared with other existing SRAM cells in terms of power, area, delay, write noise margin and read noise margin, SNM.

- I measured the leakage current and threshold voltage for 12T SRAM cell and compared with another existing SRAM cells.

- I implemented basic gates, adder, subtractor and mux using different CMOS circuits.

- I implemented a differential amplifier, operational amplifier, inverting & non-inverting amplifiers. Vivado Design Suite:

- I implemented basic gates, adder, subtractor, mux, RCA in n-bit, FSM, encoder, decoder, multipliers: booth Radix-2, Radix-4, adders: linear carry select adder, kogge-stone adder, ALU, sequence detector, shift register, D-FF, counters: jonson counter, ring counter, frequency divider circuits, RAM. Layout Using Virtuoso and Calibre:

- Using cadence virtuoso and mentor calibre tool draw the layout of basic CMOS circuits, adder, subtractor, mux, decoder, encoder, differential amplifier, operational amplifier, inverting & non-inverting amplifiers, D-Flip-flop, counter, SRAM different topology.

Critical Path Delay Improvement in Logic Circuit Operated at Subthreshold Region: Duration: July 2018 to July 2019 (M-Tech)

Working: In this project, I implemented a sub threshold digital logic circuits using mux with forward body biasing to optimize the critical path delay and energy improvement. Publication status: Paper on this project has been presented in the International Conference on Communication and Electronics Systems [ICCES 2019] to be held at PPG Institute of Technology, Coimbatore, India from 17-19 July 2019.

Smart Wheelchair:

Duration: August 2015 to April 2016(B.E)

Working: This Smart Wheelchair is working based on voice command. In this project, I used speech recognition integrated circuit for voice recognition and the wheelchair is controlled by the microcontroller. COURSES:

- Physical design (PD)

- Static timing analysis(STA)

- Design for testing(DFT)

- CMOS VLSI design

- Analog VLSI design

- Digital VLSI design

- Solid-state devices

- Memory

PERSONAL INFORMATION:

- Date of Birth: 09/08/1994

- Sex: Male

- Marital Status: Unmarried

- Languages Known: Gujarati, Hindi and English

- Nationality: Indian

DECLARATION:

- I hereby declare that the above information is true to the best of my knowledge and belief. Place: Bangalore

Date: Signature

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