North Carolina Summer Intern

BRINDITHA RAVI

Raleigh, NC

+1-201-***-**** *************@*****.*** https://www.linkedin.com/in/brinditha-ravi-b650481b0 Summary

Design Verification Engineer with hands-on experience in ASIC design, verification, and system-level validation. Successfully implemented and maintained test scripts at Harman International, and designed PCBs at Skanray Technologies. Proficient in using tools like TestRunner, Allegro PCB Design, and Diagnostic Engineering Tool (DET). Seeking to leverage expertise in RTL Design & Verification/Validation for impactful contributions starting June 2024. Education

North Carolina State University Aug 2022 - May 2024 Master of Science in Computer Engineering

The Oxford College of Engineering Aug 2018 - Aug 2022 Bachelor of Engineering (Electronics and Communication Engineering) Skills

Programming Languages: C, C++, Verilog, SystemVerilog, Python, VHDL

Working Platforms: PSpice, HSpice, MATLAB, Xilinx, Allegro Design, UVM

Design Tools: Cadence Virtuoso, Cadence/Calibre DRC, LVS tools, Questa Sim, Synopsys Virtuoso

Operating Systems: Ubuntu, Windows XP, Windows 7, Windows 10 Work Experience

Harman International May 2023 - Aug 2023

System Test, Summer Intern Novi, MI

Implemented and maintained test scripts using TestRunner Software to automate testing procedures, ensuring comprehensive coverage across all programs.

Set up and validated validation vehicles for FORD Audio systems utilizing Diagnostic Engineering Tool (DET), demonstrating proficiency in system debugging and validation.

Skanray Technologies Mar 2021 - Apr 2021

Intern Mysore, India

Designed PCB for systems using Allegro PCB Design software, enhancing practical skills in PCB layout and design

Learned industry-level medical equipment manufacturing processes, applying hardware design principles to improve design accuracy Projects

FUNCTIONAL VERIFICATION OF LC-3 -

Developing a Testbench and environment for the verification of LC-3 microcontroller

Developing components like agent, monitor, driver, generator and verified it with a predictor golden reference model and scoreboard FUNCTIONAL VERIFICATION OF I2CMB CONTROLLER -

Created an I2C BFM, layered testbench containing different components such as an agent, monitor, driver, sequencer etc., and a test plan for the functional verification of I2C multi-master bus controller

Ran verification test cases on System Verilog testbenches to achieve near 100% coverage

Performed simulations and debugging on Mentor Graphics Questa Sim ASIC DESIGN OF MULTI-STAGE DEEP NEURAL NETWORKS -

Worked on building a Deep neural network containing convolution layer which takes the input and kernel matrix and computes the input to a Relu function to saturate negative values to 0, which then passes through the max pooling layer

Conducted design validation through Modelsim simulations to ensure functionality

Used Synopsys’s DesignWare for synthesis, optimizing performance to achieve maximum efficiency per area 64 BIT (16x4) DUAL PORT SRAM -

Designed SRAM cell using 8T non precharge type cell for reducing the Energy-Area-Delay product, which is our performance metric

Verified clean LVS and DRC checks on Synopsys Virtuoso, and simulated on Questasim IMPLEMENTATION OF FLEXIBLE CACHE AND MEMORY HIERARCHY SIMULATOR -

Designed a simulator which implements write-back, write allocation and LRU replacement policy to compare the miss rate, AAT, performance, area and energy of different memory hierarchy configurations

Developed a cache module that can be used at any level in a memory hierarchy which supports any cache size, associativity and block size

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