Engineer State University

GARIMA ANAND

*******@*******.*** 716-***-**** https://www.linkedin.com/in/anandgarima

EDUCATION

State University of New York at Buffalo, New York, USA August 2015 - February, 2017 Master of Science, Electrical Engineering - Telecommunications 3.46/4.0 Apeejay College of Engineering, affiliated to MDU, India July 2008 – June 2012 Bachelor of Technology, Applied Electronics and Instrumentation 3.64/4.0 TECHNICAL SKILLS

Programming Languages: C, Python.

Wireless Technologies & Protocols: OFDMA, MIMO, GSM, UMTS, LTE, LTE-A. RF Fundamentals: RF Theory, Digital and Analog Modulation, EVM, ACPR, SNR, PAE, NF. Software and Tools: Altera Quartus II, Nios II,ns-3, Wireshark, Agilent ADS, LTSpice IV. Measuring equipment: Network Analyzer, RF generator, Function generator, DVM. ACADEMIC PROJECT WORK

LTE MODULE: To understand the LTE architecture, LTE-TDD/FDD, protocol stack, Call procedure, simulated an LTE network in ns- 3 and C++ with two e-Nodes and seven UE’s and Okumura-Hata path loss model and identified the KPI like tx mode, RSRP, SINR for uplink and downlink of PHY, MAC, RLC and PDCP level. PATCH ANTENNA: Designed and Simulated a micro-strip patch Antenna using Agilent ADS and Matlab. MIMO SYSTEM: Simulated a MIMO system with two transmitters and receivers, differential space time modulation and Jake’s fading model to generate Rayleigh fading channel. Compared the performance of the MIMO with MISO channel by plotting SER vs SNR curve in MATLAB.

OPTIMUM RECEIVER DESIGN: Simulated an optimum receiver design for AWGN communication channel using different modulation schemes (Binary PAM, 4PAM, 4QAM) to identify the best out of them by calculating and plotting the SER and BER curves in MATLAB.

OFDM TRANSCEIVER (using Intel's DE2i-150 board with Altera's Cyclone IV FPGA): Implemented an OFDM transceiver on Intel's DE2i-150 board with Altera's Cyclone IV FPGA wherein FPGA was programmed using Altera Quartus II in Verilog. FFT and IFFT were calculated using IP core. The output was shown on computer screen by interfacing the board with the screen using a VGA cable.

SERVER- CLIENT APPLICATION: Developed a server-client application (battleship game, 1 server 2 clients) on Intel’s DE2i-150 board by customizing the Nios II processor and Altera’s cyclone IV FPGA wherein FPGA was programmed on Quartus II in Verilog and Nios processor on eclipse in C. Ethernet frames over UDP for data transfer PROFESSIONAL EXPERIENCE

Jabil Global Services, India Program Engineer

Products: Alcatel Lucent Evolium 9100 GSM BTS (Transmitter Units – TRE, Antenna Units- Antenna Network Combiner, SUMA - Digital Controller), CPE-IDU-1D, CPE-ODU-PRO Radio Unit (Alvarion), SAF-LM ODU Radio Unit, Access Points (Ruckus Wireless)

• Worked as a Program Engineer towards the testing, troubleshooting and hardware development of Analog and Digital circuits at the system level with the AMS department of Jabil in India.

• Developed a comprehensive repeatable process for the testing and troubleshooting of the telecom equipment using schematics and proprietary test zigs.

• Tested RF parameters such as RSSI, Tx Power, Gain, VSWR, EVM, ACPR, PAE

• Provided end to end solution to the customer requests & issues.

• Productized the testing procedure for commercial use by comprehensive documentation of testing and diagnostic processes, test-set up, component bill of material (BOM), and work instructions quality system (WIQS). PUBLICATIONS

• LTE and Voice over LTE – IJECT, Vol 5.4-1, Oct - Dec 2014

• SDH- Legacy and Scope- IJECT, Vol 5.3-1, July – Sep 2014 Oct 2014 – June 2015

July 2012 - April 2014

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