Ranadhir Bharadwaj

Apt ***, *** E San Fernando, San Jose, CA-95112 Mobile: +1-669-***-****

https://www.linkedin.com/in/ranadhirbharadwaj acykgr@r.postjobfree.com

Objective:

Seeking a Full time/Internship position as a ASIC/FPGA Engineer

Education:

Masters in Electrical Engineering, San Jose State University, 3.4 GPA Aug14-Dec16

Bachelors in Electronics & Communication, Kakatiya Institute of Technology & Science Warangal, 3.9

GPA Sep07-May11

Course Work:

Semiconductor Device Theory Linear Systems Advanced Digital System Design & Synthesis Digital Design for

DSP/Comm.

Analog Mixed IC Signals ASIC CMOS Circuits Computer Architecture High Speed CMOS Circuits SOC

Architecture

Skills:

Programming Languages: Embedded C, C++, Verilog, System Verilog, UVM, Matlab Scripting.

Skills: Digital Design, Logic Synthesis, Place and Route, Static Timing Analysis, Computer Architecture, ASIC Design Flow

Tools: Cadence Encounter, Cadence Virtuoso, XILINX ISE, Matlab, Synopsis Design Compiler, Synopsys VCS

Bus Protocols: APB, AHB, AXI, I2C, PCI, SPI, CAN, LIN, KWP2000, PCIE, PCI

Scripting Languages: Perl, Python

Test Environment & Tools: MATLAB, Simulink, CANoe, CANalyzer, Jtag Debug, GCC Compiler

Communication Protocols: CAN, RTOS, Telematics, Bluetooth, RF, Zig-bee, SPI

Configuration Management: IBM Rational Doors, SVN

Standards: ISO 26262, MISRA C

Professional Experience:

Embedded Software Engineer at Hyundai Motor Company (R&D Centre INDIA) C, MATLAB, CANoe, CANdb++INCA Jul 2011-

Aug 2014

Development Simulation, Verification and Algorithm Code Generation of Immobilizer Electronic Control Unit ECU Software

Creating Simulation Setup in Canoe, Test case generation and Verification, Software requirement validation

Benchmarking of Electrical/Electronic Features through component level Analysis & Scenario Dev Optimization & Reusability

Power train core electronics ETAS INCA Engine control unit hardware development, EEPROM programming and issues debugging

tools ETAS INCA V 6.2/7, CANoe CAN Analyzer and Flexscan (Communication software for the engine control unit and the

immobilizer for communications data and diagnostic trouble code data. Tools for testing includes oscilloscopes, Multimeters and RLC

bridges

Academic Projects:

Design and Implementation of a Low Power UART. Verilog Synopsys Design Compiler, VCS, Primetime PX

Sep 2016

Implemented various low power techniques, designed a low power synthesizable module for an UART. Implemented and analysed

various power reduction techniques and obtained a 15% power reduction using Coding and Clock Gating Methods

FPGA: FIR filter Design on Altera NIOS II processor as Altera DE1 FPGA Quartus II, QSYS, Altera DE1 board, MATLAB

May 2016

FIR filter is designed and implemented on DE1 board using NIOS II processor, JTAG UART, on-chip memory, performance counter

using Altera QSYS on DE1 board as a hardware accelerator

Compared performance between software-only FIR filter and hardware-accelerated FIR filter in terms number of clock cycles

FPGA: Design Five stage pipelined Nios II MIPS processor Verilog and C Aug 2016

Design and synthesized a 32 bit MIPS processor with a five stage Pipeline. Programmed and verified the functionality of MIPS

Processor using verilog considering area, time and power constraints.

Design and implementation of RTL for LPC2478 LCD controller SystemVerilog

Apr 2016

Designed AHB master and slave interface for writing data into and reading data from memory FIFO, Designed timing controller,panel

clock generator, pixel serializer and RAM palette internal blocks. Controller provides support for TFT LCD panel with 1, 2, 4, 8, 16

and 24 bpp configuration. Successfully synthesized design at 300MHz.

Implementation of Low Power Input Feed Forward Delta Sigma Modulator (Matlab, Cadence Spectre 45nm Technology) Nov 2015

Timing constraint is identified by simulation and draws backs of Analog adder is plotted by the actual topology & proposed topology

of CIFB and CIFF, designed schematic & standard cell layouts using Cadence Spectre, Virtuoso, Performed LVS, DRC checks,

Layout, simulations using Assura extract, abstraction of cell view

Design of a 32 bit RMS value calculator Verilog Aug 2015

The purpose of this project is to design, optimize and analyse a simple 8-bit scalar processor. Implementation work includes the details

of design, implementation, tests, measurements, analysis, design options with design limitations

Optimized Design Layout, Synthesis and Functionality verification by simulating schematic

Performance Evaluation of Storage Device Python Spring'15

Developed a script that evaluates the performance of Solid State Device using Python.

Performance evaluation was done by measuring the bandwidth, latency, IOPS, CPU Utilization of different modes of accessing data

and stored in log files and performance was compared based on modes of operation.

Activities/Awards:

San Jose State University Housing services Worked as Office Assistant 2015-2016

Hyundai Motors R&D - Awarded Grade-1 Engineer, Basic Korean Language Certification, PLM Training

2012

Robert Bosch Germany - Training on PCB assembly of SMARTRA6 at BOSCH, INDIA for Automotive Electronics

2012

Contact this candidate