Principal Hardware Engineer

Lydia L. So

**** ******** ***, *********, ** ****4 408-***-****(C) 408-***-****(H)

*********@*****.*** Status: U.S. Citizen

CAREER INTERESTS

A challenging software development position in computer-aided design

(CAD), specified in extraction, timing, physical design optimization and layout generation for advanced chip and microprocessor design. EDUCATION

Ph.D., EE, Cornell University, 1991

B.S., EE, University of Illinois at Urbana-Champaign, 1986 WORK EXPERIENCES

Oracle Corporation, Processor CAD Division Santa Clara, CA Principal Engineer Jan 2010 – Feb 2017

• Developed and supported an in-house layout generation tool for Cadence Virtuoso-XVL; Wrote power grid router in C++, OA and SKILL; Achieved 100% route-ability and DRC clean layouts for std and SRAM cell libraries in 7- and 10-nm TSMC process nodes

• Developed and supported an in-house dummy cell insertion flow to improve layout quality and DFM

• Implemented test and regression methodology including auto- layout generation, LVS, RC extraction and spice-simulation Patent: Method and apparatus for dummy cell placement management Patent number: 9330224 (granted April 30, 2014)

Sun Microsystems, PCAD/Microelectronics Division Santa Clara, CA Sr. Staff Engineer Mar 2003 – Jan 2010

(1) Lead, Deployment of Design Optimization Jan 2008 – Jan 2010

• Implemented multiple threshold voltage (multiVT) optimization flow (perl/tcl) for power, performance, and area

• Developed, integrated and supported new features to the optimization flow for multiple projects

• Coordinated development, customer support and flow update releases; Resolved project specific issues within releases

(2) Lead, Extraction Team Mar 2003 – Jan 2008

• Coordinated development and support of overall extraction methodology for 65nm/45nm technologies for back-end analysis and verification tools/flows

• Led parasitic extraction flow development, supporting hierarchical/flat extraction methodology for power grid, signal electro-migration (SigEM/EMIR), clock net extraction

• Developed methods for capacitance and resistance accuracy benchmark with QuickCap and Raphael

• Implemented regression and integrated testing methodologies SandCraft, Inc, CAD Division Santa Clara, CA

Group Leader Aug 1998 – Mar 2003

Worked on multi-faceted circuit and physical analysis tools for high- speed microprocessor design including methodology definition, scripting, testing

• Developed RC parasitic extraction flows based on Mentor xCalibre, Quickcap and Raphael

• Performed on-chip inductance simulation and analysis using Raphael 2D and 3D field solvers

• Developed/supported transistor-level static timing analysis flow

• Provided customization, bring-up and support of Simplex-based clock skew, power grid and signal electro-migration analysis flows such as ClockStorm, ElectronStorm and VoltageStorm Winbond Microelectronic Corp, NVM Division Santa Clara, CA Project Leader Jan 1997 – Aug 1998

Performed TCAD process/device simulation, calibration, and optimization for FLASH and EEPROM technologies, capacitance modeling, device characterization, and SPICE compact model development for NVM applications; Worked on design rule analysis, process porting, shrink technologies, SPICE modeling issues

Siliconix, Design Concepts Division Santa Clara, CA Staff engineer Sep 1995 – Jan 1997

SPICE Compact model extraction and validation of 15 & 60-volt BCD

(Bipolar-CMOS-DMOS) process for power IC applications Stanford University, CIS Palo Alto, CA

Postdoc Visiting Scholar Jan 1992 – May 1995

Supervisor: Prof. Robert Dutton

Principal code developer of PISCES-2ET, a dual energy transport model which included carrier energy balance equations and lattice heating; Applications including hot-carrier effect in deep submicron MOSFETs, and self-heating effect in SOI

SKILLS

Programming languages: Perl, Tcl, C++, OpenAccess, SKILL EDA tools: Cadence Virtuoso, Calibre, XCalibre

PROFESSIONAL AFFILIATIONS

IEEE Member; Member of Tau Beta Pi; Member of Alpha Lambda Delta REFERENCE

Available upon request

SELECTED PUBLICATIONS

1. Z. Yu, D. Chen, L.L. So and R. Dutton, PISCES-2ET User's Manual, Stanford University, August 1994.

2. L. So, Device Simulation and Calibration for SOI, CAD for IC's - Process, Device, Circuit, and Virtual Factory, Stanford University, Stanford, CA, Aug. 15-16, 1994.

3. L.L. So, E. Kan, Z. Yu, and R. W. Dutton, Self-consistent Approach to Substrate Current Simulation in Submicron MOSFETs, EDMS, Hsin-Chu, Taiwan, ROC, July 15-17, 1994.

4. L.L. So, D. Chen, Z. Yu and R. W. Dutton, Dual Energy Transport Model for Coupled Lattice and Carrier Systems, TECHCON 93, Atlanta, GA, Sept., 1993.

5. L.L. So, D. Chen, Z. Yu, and R.W. Dutton, Improvement of Initial Solution Projection in Solving General Semiconductor Equations Including Energy Transport, International Workshop on Simulation of Semiconductor Processes and Devices, SISDEP, Vienna, Austria, Sept. 1993.

6. L. So, PISCES Examples for MOS and Bipolar Devices, CAD for IC's - Process, Device, Circuit and Virtual Factory, Stanford University, Stanford, CA, Aug. 2-4, 1993.

7. L. So, D. Chen, Z. Yu, and R. W. Dutton, Robust Simulation of GaAs Devices Using Energy Transport Model, 1993 International Workshop on VLSI Process and Device Modeling (VPAD) Digest, pp.32-33, Nara, Japan, May 14-15, 1993.

8. K. C. Wu, Z. Yu, L. So, R. W. Dutton, Robust and Efficient AC Analysis of High-Speed Devices, IEEE IEDM Digest, pp 935-938, San Fran., CA, Dec 1992. pp.99-102, Urbana, IL, May 1992. 9. L. So and C.A. Lee, Verification of generalized telegraphist's equations for various dielectric waveguides, Appl. Optics, 31, 6446- 6452, (1992).

10. L. So and C.A. Lee, A new integrable optical modulator-switch optimized for speed and power consumption, J. Appl. Phys. 66, 2200- 2205, (1989).

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