MONISHA NAIDU

** ******** ** **** ****, San Jose, California 95134

M: +1-469-***-**** Email: acy08v@r.postjobfree.com LinkedIn: www.linkedin.com/in/monishanaidu Graduate seeking a Full Time position in the field of VLSI/ Physical Design/ Digital System Design where I can utilize my skills and gain further experience while enhancing the company’s productivity and reputation. EDUCATION

Master of Science in Electrical Engineering GPA 3.4/4 UNIVERSITY OF TEXAS AT DALLAS, TEXAS, USA May 2016 Coursework: Advanced VLSI, VLSI Design, Advanced Digital Logic, Design Automation, Computer Architecture, Trusted & Secure IC’s and Systems, RF and Microwave systems engineering, Optical Communication Systems, Microprocessors and HDL. Bachelors of Engineering in Electronics and Communication CGPA 9.02 /10 DR.AMBEDKAR INSTITUTE OF TECHNOLOGY, BANGALORE, INDIA June 2014 Related Coursework: Digital System Design using Verilog, Fundamentals & Design of Logic Circuits, Embedded System Design, Real Time Operating Systems, Microprocessors, ARM Processor SKILLS

Programming Languages : C, C++,Perl

Hardware Languages : Verilog,VHDL,MATLAB

EDA Tools : Cadence Virtuoso, Encounter, Design Vision, Prime Time, Xilinx ISE14.1, HSpice, Virtual Photonics, NI AWR Design Environment, SiliconSmart, Waveview EXPERIENCE

Standard Cell Design Intern September 2016-Present Nangate Inc, Santa Clara, CA

Design of standard cell library - 180nm TSMC Foundry, 55nm Global Foundries, 14nm SMIC Foundry. Tools used: Nangate Library Creator for Layout design, Calibre for DRC and LVS check. ACADEMIC PROJECTS

Design and Layout of 8T SRAM Memory Array using IBM 130 nm technology Summer 2015

Designed a 256 word Memory array of 8T memory cells with distinct read and write bit lines to enable simultaneous read and write operation on different memory locations.

Designed peripheral circuits- Decoders, pre charger, write driver, clock buffer and sense amplifier, each sized considering the load capacitances and logical efforts on the path.

Manual placement and layout was done in Cadence Virtuoso with minimum total area. DRC, LVS were verified.

HSPICE was used to check the functionality and to measure the worst case read and write times of the memory. ASIC Design flow of a 20 BIT ALU using IBM 130nm technology Fall 2014

Arithmetic and Logic Unit performing 21 operations was designed and coded in RTL Verilog.

Standard cell library- INVERTER, AOI22, MUX 2:1, NAND2, XOR2, NOR2, OAI3221, D Flip-Flop cells were created and characterized using Siliconsmart.

Verilog code was synthesized using the generated .lib file. Cadence tool, Encounter was used to perform Automatic place and route of the final design. DRC, LVS were verified.

Static Timing Analysis was done using Primetime to find the worst case delay. Implementation of Simulated Annealing based partitioning algorithm for automatic placement and routing

Implemented circuit bi-partitioning algorithm with an objective of minimizing the cut size considering area balance criteria.

Implemented a placement algorithm to minimize the wire length. The algorithms were written in C++ and tested on standard IBM benchmarks..

Hardware Trojan design in AES-Cryptosystem Spring 2015

Spartan-3E FPGA board was used to implement a set of 5 Hardware Trojans into an AES-Cryptosystem, codenamed ‘Alpha’. Validation of the cryptosystem was done by passing the Trojan to an extensive set of tests. Resource utilization of the Trojan infested design and the benign was close as expected. Design of Cache hierarchy of an Alpha Microprocessor Spring 2015

Verified performance parameters such as CPI and cost of usage of the cache for various replacement policies such as FIFO, Random and LRU (Least Recently Used).

Benchmarks such as GCC, Go-Alpha and Anagram for the above policies were run and the statistics for verification were collected through the Perl script.

PUBLICATIONS

[1] Monisha Naidu, Dharani Manju H V, Lakshmi S, Pooja M K. “Advance Security System for Automobiles using Flexray”, Institute of Research and Development, India, Volume-2, Issue- 6,7, Pg 30-33, 2014. ISSN (Online): 2347-2812

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