Shih-Yu Huang

*** ******* **. ********, ** *****

Tel: 408-***-****, Email: acxxfj@r.postjobfree.com

OBJECTIVE

Seeking a challenge physical design/timing technical position in CPU/SoC/ASIC design

QUALIFICATION

15 years experience of complex high end multiple cores server microprocessors physical

design and timing closure through tape out with depth physical design knowledge and

strong technical skill.

Excellent communication skills and team worker.

EXPERIENCE

Oracle Corp. 2010 - Present

SPARC 10 nm/16 nm/28 nm high end server microprocessors

SoC full chip integration: 24 cores SoC full chip top level floor plan, routing, pins

placement, repeaters insertion, design optimization and timing closure. Plan routing

resource and route SerDes source synchronous paths in ICC with attention of clock

shielding, duty cycle degradation. Route high clock frequency domain interface in ICC

with optimized repeaters insertion. Communicate with block owners full chip floor plan,

full chip routing plan, block pins placement to achieve full chip routing and timing goal.

SoC full chip static timing analysis and timing closure: Full chip timing closure with

methodology for timing closure flow, full chip incremental repeaters insertion flow.

Performed full chip PrimeTime static timing analysis with AOCV, different PVT corners

and different StartRC extraction corners. Developed and implemented timing constraints

(SDC). Identified full chip timing solutions and worked with block owners and full chip

integration team to achieve full chip timing closure goal.

Block level composition: Work with clock/full chip timing/full chip integration teams to

come up with full chip channel flop banks solution and write initial Verilg RTL. Flop

banks composition include floor planning, block level placement and routing in ICC,

block pins placement, scan chain order, test logic synthesis by Design Compiler, Cadence

Conformal LEC verification, power grid design, clock planning and routing, StarRC

extraction, physical design verification (LVS/DRC by Calibre) and implement ECO to fix

timing/EM/IR/Noise.

Clock verification: Block level post layout Spice accurate clock skew analysis from full

chip global clock buffer to blocks flops input clock. Reviewed clock buffers placement

and routing inside block and identified clock buffers sizing solution so all flops skew

difference met block clock skew requirement.

LSI Corp. Hard Disk drive read channel, Viterbi detector ASIC design 2005 -2009

40 nm, 10 Tap FIR Digital Filter: From the beginning of the project, used Spectre and

HSPICE to evaluate max speed with different transistor channel length, Vt, and PVT for

a 10 tap digital filter with Radix4 Booths algorithm multipliers, carry save adders.

Synthesis (Design Compiler); static timing analysis with special attention to high Vt cells

could slower at temperature -40C instead of 125C (temperature inversion phenomena in

advance technology); power analysis (Ultrasim) with attention to max power

consumption at temperature 125C ff process corner.

90 nm, 2.1 GHZ Viterbi detector top level integration and timing closure: This task

includes integrating synthesis blocks (digital filters) and semi-custom blocks (branch unit,

trellis, path memory) together and using Synopsys Pathmill for static timing analysis also

generating timing model (lib file) for whole Viterbi detector, Cadence PacifIC for device

and interconnect coupling noise analysis, Cadence Ultrasim for dynamic timing analysis

to confirm with static timing analysis result.

Intel Corp.

65 nm Centrino dual cores mobile CPU, Yonah circuit design Feb. 03 ~ July 05

Register file design

16 entries x 64 bits array with 1 write port and 2 read ports. Checked power race

condition to avoid power consumption in overlapping period of precharge & evaluate

phase. Arranged word lines write & read enable & shielding to reduce Miller Coupling

Factor for speed and cross coupling noise fix. Bit lines shielding for cross coupling noise

fix and increased keeper size for propagated noise fix but should not increase too big to

avoid write ability issue. Long channel device on pull down stack to avoid leakage noise

and for power saving purpose. Inserted long channel device in P MOS word line drivers

to reduce leakage power based on known parking state knowledge.

Itanium processor family, Montecito design verification Feb. 02 ~ Jan. 03

(1) Register file RTL vs. schematic formal verification

Converted netlist into RTL code and generated boolean equation to verify function

equivalence. Captured several improperly connected schematic issues.

(2) L2 cache design verification

Wrote IA64 assembly tests to test multi-threading feature and L2 cache function. Tasted

MESI cache coherence protocol, LRU algorithm, read & write throughput by monitoring

RTL behavior on every cycle. The tests captured several RTL bugs.

Itanium processor family, Merced DFT May 00 ~ Jan. 02

Sequential ATPG algorithms due to timing and area constrains. Made complex gate level

models CPU blocks and validated their logical integrity. Wrote IA64 assembly language

focus tests and merged with ATPG result to bring several Merced blocks to high fault

coverage.

COMPUTER SKILLS

VLSI Tools: Verilog, ICC, Design Compiler, PrimeTime, Cadence Virtuoso, Cadence

Conformal LEC, StarRC, HSPICE, Calibre, Pathmill, Prime Power, Nanosim, ModelSim,

Spectre, Ultrasim, Perl, Tcl, awk

EDUCATION

M.S. Electrical Engineering, University of Southern California Sept. 98 ~ Dec. 99

REFERENCE

Available upon request

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