SAGAR CHANDRA

Phone: 970-***-**** e-mail: acxu8n@r.postjobfree.com Linkedin Profile: www.linkedin.com/in/sagarchandra89 Recent Graduate Electrical Engineer looking for new and exciting opportunities in the VLSI domain EDUCATION

Master’s in Electrical Engineering, May 2016 GPA: 3.22 Colorado State University, Fort Collins, Colorado, USA COURSES: VLSI System design, Digital Systems Design, Radio-frequency Integrated Design, Advanced Computer Architecture, Embedded Systems Design, Internet engineering, Micro-electro Mechanical Systems, Semiconductor Physics Bachelor’s in Electronics and Communication Engineering, Jan 2012 JSS Academy of Technical Education-VTU, Bangalore, India TECHNICAL SKILLS

Hardware Description Languages: VHDL, Verilog

Tools: Cadence Virtuoso, Altera Quartus, Spectre, Layout-XL, Encounter, Assura, MATLAB, Eclipse, NC-Verilog Skills: CMOS, SoC, ASIC, Digital Circuit Design, Logic Design with Verilog or VHDL, Schematic Capture and Circuit Layout, RTL Design & Verification, Static Time Analysis (STA), Netlist to GDSII, Physical Verification-DRC, LVS Check, Parasitic Extraction, and Simulation

Scripting Languages: Perl, Python

Equipment: Digital Scopes, Oscilloscope, Logic Analyzer, Spectrum Analyzer Programming Languages: C, C++, Java

Operating Systems: Linux, Windows

EXPERIENCE

Design Engineer, Jan 2012 – May 2014

Vision Tech Systems, Bangalore, India

Responsible for design, development and testing of LED display systems

Organized and executed design projects in accordance with customer timetables

Created test-bench, used testing equipment, soldering in developing LED display systems PROJECTS

Physical design – Digital IC design of a 4:1 MUX, Feb 2016

Designed a 4:1 MUX IC using TSMC 180nm CMOS process technology for 0.9V Supply and the logic to drive load capacitances ranging from 700-850fF and 850fF-1pF

Performed Transistor sizing, Output Matching and Layout Planning and Routing

Completed Design Rule Check (DRC), Layout vs Schematic (LVS) & Quality Rule Check (QRC) for verification of Design Physical design – 8-bit synchronous 2’s complement Adder/Subtractor, May 2016

Designed an 8-bit Adder/Subtractor for a 1 Mhz clock using TSMC 180nm CMOS process technology for 0.9V Supply and ran Static Time Analysis (STA) in Cadence Encounter timing system

Cascaded to do a 16-bit addition/subtraction and used carry select algorithm

Used NC-Verilog to change the schematic into a Verilog netlist and imported it into Encounter to perform routing

Completed floor planning, place and route, and ran DRC, LVS and QRC for verification and parasitics extraction Digital Circuit Design/RTL Logic Design and Simulation – Multipliers and Counters, Oct 2014

Design and implement 1-bit ALU cascaded to form a 3-bit ALU to implement add, subtract, XOR and shift operations

Logarithmic Multiplier to multiply two 5 bit numbers (Involved design of carry look ahead adder for addition, ROM with 64 entries for log table and antilog table lookup)

Sequential logic design of Grey code counter in cadence using D-flip flops

Pulse clock generator and Pyramid counter in Verilog Digital Circuit Design/RTL Logic Design and Simulation, Nov 2014

Design and implementation of a Subway logic and Four way traffic light controller using Finite State Machine

Designed the controller using finite state machines and used state reduction techniques for simplification of states

Implemented the design in Cadence Virtuoso using schematics entry and simulated it in Quartus using Verilog Advanced Computer Architecture, Oct 2015

Implemented Filters, Vector Reduce Algorithm and Histogram Algorithm on GTX 480 NVIDIA card using CUDA C Implementation of various On-Chip VLSI Circuit Design Styles, Mar 2016

Mapping different Logic functions to Conventional Static CMOS, Pseudo-nMOS, Cascode Voltage Switch Logic (CVSL), Domino CMOS and Pass Transistor Logic by optimizing them for performance, power, delay and noise margin Radio Frequency (RF) Integrated Circuit Design, Nov 2015

Implemented a receiver for Bluetooth in 180nm tsmc18rf technology which consisted of a two-stage Low-Noise Amplifier

(LNA), Mixer, Filters and an Oscillator for 1.8V supply with receiver frequency of 2.4GHz-2.48GHz Construction of a simplified DHT network (Structured and Unstructured P2P network), Feb 2015

TCP/IP and UDP server/client model on multiple nodes

Searching contents in a Distributed Application-Layer Network with 80 nodes

Extended the project to Distributed Hash Table based Content Searching using the chord algorithm