RESUME

LALIT KUMAR SINGH contact: #+918*********

Email id:acx2lh@r.postjobfree.com

Address- 22, First Floor Gautam Nagar,New Delhi: 110049

CAREER OBJECTIVE: As a dedicated and highly motivated Electronics Engineer, I would like to become a “RTL DESIGN” Engineer and a good HDL programmer.

EDUCATIONAL QUALIFICATION:

B.Tech with aggregate 73% in “Electronic and Communication” from Inderprastha Engineering College, Ghaziabad (2016 pass out).

12thwith aggregate 83.8% from Bhupati Singh Memorial Inter College.

10thwith aggregate 65.5% from Krishna Chandra Ram Chandra Inter Collage, Sultanpur .

SUMMARY:

Good understanding of Digital logic Design and Implementation using Schematics design

Knowledge of FPGA Architecture and Its working.

Hands on knowledge in FPGA Synthesis, Implementation, Real Time debugging and Simulation tools.

Good Knowledge of C and C++ Programming.

Knowledge of programming in SYSTEM VERILOG.

Digital Signal Processing and implementation on FPGA using FPGA Tools.

Hanson knowledge of HDL (VHDL/Verilog).

Understanding of serial communication protocols (I2C, SPI and UART).

Proficient in simulation at both Modelsim and ISim simulator.

Experience in writing testbench for both VHDL and verilog HDL.

Good knowledge of static timing analysis (STA).

EXPERIENCES:

6 months experience in comcon technologies.

1.3 years experience as a trainee from pine training academy Ghaziabad regarding to following topics:-

Advance knowledge of DIGITAL ELECTRONICS.

Learnt both hardware languages and did project on both in vhdl and verilog as well.

DSP at system generator.

TECHANICAL SKILLS:

SOFTWARE SKILLS:

Languages : C language

Operating Systems : Windows 8/7/XP/2000

Microsoft Word, Power Point, Excel.

HARDWARE SKILLS:

HDL - VHDL/Verilog Language.

HDL Simulation tool -Xilinx ISIM /Altera Modelsim.

HDL Synthesis tool -Xilinx XST, Altera 13.1

HDL Implementation tool -Xilinx Project navigator,QUARTUS-II

FPGA Architecture -Artix -7,Spartan-6 and Cyclone-IV

FPGA Board Exposure -Nexys 4 based on Artix -7 by Digilent,

-ep4cgx150df31c7and ep4cgx50df27c7

Platform -Windows 7

PROJECTS

1.8 CHANNEL SDI IP INTSTANTION AT ALTERA QUARTUS-II CYCLONE-IV GX DEVICE

Description: FPGA family- cyclone iv

Device name – ep4cgx50df27c7

Clock frequency - 50 MHZ

Operating voltage - 3.3 V

Working: I created SDI IP with the help of ALTERA mega core SDI user guide and also found problem while I was using it regarding with reconfiguration IP and took support from altera forum by MR. Ching Pee and configured it. I used 7 SDI IP with triple standard video (SD, HD and 3G standard) and then interfaced it with LVDS and ALTERA BUFFIO IP.

2. INSTANTIATION OF DDR3 HARD IP ON CYCLONE-IV BOARD.

Description: FPGA family – Spartan-6

Device name - xc7a100t-1csg324

Clock frequency - 100 MHZ

operating voltage - 3.3 V

Working: I wrote vhdl code for DDR2 SDRAM controller with the help of user guides and FSM. Firstly I read about the precharge and refresh condition because I was finding difficulties when designing the FSM for controller. Then found out the timing data regarding the refresh time and CAS latency.

3. AM MODULATION AND AM DEMODULATION USING SYSTEM GENERATOR

AM modulator and receiver of an audio signal at a sampling frequency of 8 KSPS, carrier frequency of 10 MHz and sampling rate of 50 MSPS have designed in this project. This designing has done by using Xilinx DSP blocks.

Tools used: MATLAB, System Generator.

Working:

INTERPOLATION: In interpolation firstly up sampled the signal by 6250 factor in 6 steps of 2,5,5,5,5,5 by using FIR filter .

DECIMATION: IN decimation further down sample the received signal by 6250 in 6 steps 5,5,5,5,5,2 using FIR filter.

4 .DIGITAL MODULATION (ASK,FSK,PSK) AND DEMODULATION USING SYSTEM GENERATOR

ASK:- In ask modulation used a multiplexer which is selecting a sine wave having amplitude one and when select line is equal to zero which is connected to a Bernoulli sequence generator and amplitude is 1two when select line is holding 1.

FSK:-In FSK multiplexer is selecting high frequency signal when select line is one and selecting low frequency signal when select line is equal to zero.

PSK:-In PSK modulation mapped the I and Q values by multiplexer and then convert it into the imaginary signal and passed it from AWGN channel and then use complex to real signal and remapped and again received the given signal.

Tools used: MATLAB, System Generator.

5 .PROJECT ON RTL“DIGITALCLOCK” USING DIGITAL COMPONENTS

Description: Digital clock: Purely synthesized RTL code implemented on Artix-7(Xilinx part number XC7A100T-1CSG324C) board using VHDL Code.

Specifications :-

1) Operating frequency - 100 MHz

2) Operating voltage - 3.3 v

3) Reset button at any time which resets the clock to 00:00:00

4) Set button available for Hours,Minutes and Seconds

5) Time in the 24 hour format as HH:MM:SS

Tools : XILINX ISE Design suite 14.7

Working: Firstly convert 100 MHZ frequency in seconds, minutes and hours by RTL code and converted it into BCD format for displaying at seven segment display. Forward this BCD format into anode pins through multiplexer and display it at cathode.

(6). IMPLEMENTATION OF RTL “STOP WATCH” USING DIGITAL COMPONENTS.

Description: stop watch with pause and reset button on Artix-7 using VHDL code.

FPGA family - Artix-7

Device name - xc7a100t-1csg324

Specifications :-

Clock frequency - 100 MHz

Pause and reset signal - on board push button

Output -SEVEN SEGMENT display

Format : MM:SS:MILLISEC

Software : ISE Design suite 14.

Working: Firstly I wrote the VHDL logic code for state machine which was basically for pause and further increasing the counts of stop watch and then send it from Binary to BCD in order to display it at Seven Segment Display.

7. LED SEQUENCE GENERATOR” USING FPGA COMPONENT (BLOCK RAM).

Description: FPGA family - Artix-7

Device name - xc7a100t-1csg324

Clock frequency - 100 MH

Output -LED

Operating voltage - 3.3 V

Working: Firstly I generated BLOCK RAM by using core generator then interface the signal by VHDL coding and generated UCF file by input and output interfacing and generated bit file and burn through -Nexys 4 based on Artix -7 DIGILENT BOARD.

(8). “REPRESENTATION OF ALPHANUMERIC CODE” ON SEVEN SEGMENT DISPLAY USING FPGA COMPONENT (BLOCK RAM).

Description: FPGA family - Artix-7

Device name - xc7a100t-1csg324

Clock frequency - 100 MHZ

Output –Seven segment display

Operating voltage - 3.3 V

Working: In this project firstly I generated BLOCK RAM by core generator and then wrote VHDL code in order to generate the output of BLOCK RAM then made a Binary to BCD converter in order to display it on cathode display and then generated UCF file by input and output interfacing. After ucf file generated bit final file and burn it on Nexys 4 based on Artix -7 by Digilent.

(9). SINE WAVE GENERATION BY VHDL CODE ON ALTERA

Description: FPGA family – Cyclone-III

Device name – EP3C25F324C7

Clock frequency - 50 MHZ

Output –Sine wave

operating voltage - 3.3 V

Working: While generating sine wave I wrote VHDL code for the given look up table of sine wave and then passes this wave from FPGA to DAC and shown at oscilloscope.

AREA OF INTEREST:

Digital Electronics.

HDL programming (VHDL/Verilog).

C programming

EXTRA CURRICULAR ACTIVITIES:

Participated in Robotics competition organized by GENTRONIX (AN ECE FORUM).

Participated in ENGINEERING DAY QUIZZ 2015.

PERSONAL DETAILS:

•Father’s Name : Mr. Dhirendra singh.

•Date of Birth : 14th Aug 1994.

•Language known : English and Hindi

(Reference available on request)

Place: LALIT KUMAR SINGH

Date :

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