David Zhang

**** **** **, *******, ** *****

408-***-****, 408-***-****

acvxge@r.postjobfree.com

Objective:

A circuit design (analog/mixed signal) position in semiconductor industry.

Summary of Knowledge and skill:

Transistor level design analog/mixed signal CMOS circuit, including

ADC/DAC, PLL/DLL, voltage regulator LDO, bandgap reference, amplifier,

comparator, temperature sensor, high voltage charge pump, high speed serial

interface

Power analysis, IR drop measurement, power plan

Layout floor plan and guide to layout designer

Design Reliability verification, EM/SH and physical verification

Interface between circuit and RTL

Post silicon validation

CAD, tool and equipment skill:

Schematic and simulation tools: Cadence ADE, Virtuoso, Calibre,

spectre/Spice,

Ultrasim/Nanosim, Synopsys XA (fast Spice), Matlab, post layout extraction,

Synopsys StarRC,

post layout simulation with parasitic, POLO, LVS/DRC.

Design reliability verification: NOVA/Monte Carlo, EM/SH and Aging.

Timing lib: Cadence tool, as timing interface between circuit and RTL.

Silicon test and debug in a lab environment: Bench test using different

equipment

Professional Experience:

Mixed Signal Circuit Design Engineer, Banpil, Inc, Santa Clara, CA (01/2015

- present)

Designed 12 bit differential SAR ADC for optical sensor. Monotonic

capacitor switching reduced 81% switching energy and 50% capacitance.

Hybrid voltage scale and charge scale DAC with 7 bit LSB resistor string

and 5 bit MSB capacitor array. Hybrid structure reduced silicon area with

less MIM capacitors, resistor string ensured monotone. No-lumped capacitor

array reduced DNL. DNL/INL achieved 0.6 LSB and 0.8 LSB. Dynamic latch

comparator reduced power to 50uW. Sampling with bootstrapped switch, Vgs of

sampling transistor fixed at VCC, improved switch linearity, charge

injection. 12 bit ADC speed is 2.5 Ms/s.

Designed curvature compensated Bandgap reference to support 12 bit

differential SAR ADC. Temperature coefficient is 7 ppm/C from -40 C to 120

C, PSRR is 80 db.

Circuit Design Engineer, Intel Corp, Hillsboro, OR (03/2002 - 12/2014)

Designed different analog/mixed signal IP's for Intel internal and external

customer by using 22nm and 14nm Intel technology. IP's include different

serial interface and sub analog circuit.

Designed Self Bias PLL, DLL used for phase interpreter, clock data recover

and Receiver with the spec on frequency, jitter, bandwidth, INL, DNL and

duty cycle.

Designed SAR, pipeline and other ADC/DAC.

Designed Bandgap reference, Voltage regulator LDO, Temperature Sensor, High

voltage charge pump.

Above analog circuits were used in Serial Interface includes PCIE(3GIO),

QPI, DDR.., for several generation and different technology from early

180nm to latest 14nm.

Wrote design documents as a part of design flow, which includes design

review, IP data book and silicon bench test report.

Interfaced with RTL design, test engineer and layout designer.

Circuit design engineer, NDSP Corp, Campbell, CA (02/2001 - 03/2002)

Designed analog circuits of Video AFE and digitizer chip, which includes

Pipelined ADC, Gain control amplifier.

Circuit design engineer, Lattice Semiconductor Corp, San Jose, CA (12/1996

-02/2001)

Designed analog/mix signal circuits for FPGA (programmable chip) including

high voltage charge pump, voltage regulator LDO, Bandgap reference and

other analog circuit.

Circuit design engineer, IMP Inc, San Jose, CA (01/1994 - 12/1996)

Designed analog/mixed signal circuits for CMOS programmable chip including

ADC, DAC and digital control circuits.

Circuit design engineer, OnChip systems, Inc, San Jose, CA (01/1991 -

01/1994)

Designed a high speed logarithm amplifier with bipolar differential

amplifier and continuous time filter.

Education:

MS Electrical Engineering, Syracuse University, NY

BS Electrical Engineering, Jiao Tong University, Shanghai, China

Reference:

Available upon request

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