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Engineer Design

Location:
Bengaluru, KA, 560001, India
Posted:
April 20, 2016

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Resume:

DEEPAK R • Mobile: - +91-998*******

• E-Mail:- acufjs@r.postjobfree.com

SUMMARY An efficient R&D Engineer(VLSI) with 1 year 8 month’s experience in designing and debugging, hands on experience on high speed interfaces micro architecture design and tackling issues related to digital design. Adept in VHDL, Verilog and C.

Good exposure to RTL Design, Synthesis and simulation debugging. Worked on AMBA AHB/APB/ASB, UART, SPI, I2C and PCI. Strong in Computer Architecture, Digital Design. Familiarity with industry standard circuit design and verification tools, flows and methodologies. Seeking a challenging position in the field of VLSI Design/ASIC Design / IC Design.

EXPERIENCE R&D Engineer(VLSI) September 2013 – June 2015 Emics Technologies

Bengaluru

ROLE 1. Provided design services to help specify develop and design ASIC and FPGA Solutions.

2. Implemented FPGA designs using Xilinx ISE in Spartan3E, Virtex5 FPGA to help customers achieve their goal of first time to market cost reduction.

3. Optimized FPGA designs for high throughput, low latency and timing. PRESENT Handling BE/M.Tech projects.

SKILL SET Electronic Design Suite

Synopsys VCS/Design Compiler, Cadence, Xilinx ISE Design Suite, QuestaSim, QuartusII, HSpice, BSpice, Simulink, and Magic Programming Languages

C, Verilog, VHDL, and PERL.

FPGA Board

Virtex 5, Sparten 3E, Altera Cyclone DE-II.

Familiar Protocols

AMBA APB/AHB/ASB, UART, I2C, CAN, SPI.

Familiar OS

MS-DOS, Windows, Linux RED HAT, Ubuntu.

EDUCATION Master’s in VLSI-CAD,2013 PERSONAL DETAILS MAHE, Manipal DOB: - 24 JAN 1988

BE in ECE,2011 LANGUAGES KNOWN

SJCIT, Chickballapur English, Kannada, Telugu, Hindi

• Address: -3rd Cross, Sadashiva Badavane Gowribidanur, Karnataka State, India PROJECT DETAILS

Project #1 FPGA IMPLIMENTATION OF ADVANCE ENCRYPTION ALGORTIHM

Role Team Member

Details The AES based on the Rijndael Algorithm is an efficient cryptographic technique that includes generation of ciphers for encryption and inverse ciphers for decryption. This project presents the AES algorithm with regard to FPGA and the Verilog HDL.

Responsibilities 1. Developed conceptual flow graph and algorithm for generic design of AES. 2. Developed Functional Blocks for Encryption Methodologies like row shift, Column mixing.

3. Developed architecture for polynomial multiplication. 4. Involved in developing different modules for cipher multiplication, substitution Matrix.

5. Decryption also performed for verification of design. 6. Developed Verilog test benched for design.

7.Developed different scenario for testing of design. 8.Tested design on FPGA.

Environment: - Verilog HDL. Tools: - Xilinx ISE Design suite. Hardware: - Virtex5 Project #2 IMPLEMENTATION OF AMBA AHB PROTOCOL FOR HIGH CAPACITY MEMORY MANAGEMENT.

Role Team Member

Details Protocol is implemented for multi master and multi slave communication using arbiter and decoder. Max 16 master and slaves can access the bus depending priority level decided in arbiter. Implemented for burst transfer between BRAM, DAM & processor.

Responsibilities 1. Detailed study of documents related to AMBA AHA developed by ARM 2. Detailed study of different hardware architecture to develop Master control.

3. Thorough study of micro architecture design in Verilog. 4.First designed for single master and two slave communication. 5. Developed RTL Design for Arbiter for priority resolution Environment: - Verilog HDL. Tools: - Xilinx ISE Design suite. DECLARATION

I here by declaring that the information Furnished in the resume is correct to the best of my knowledge

DEEPAK R

• Address: -3rd Cross, Sadashiva Badavane Gowribidanur, Karnataka State, India



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