G.JYOTHI
Shanthi nagar, kukatpally, Ph no:812*******
Hyderabad -500072. Email:******.*.**@*****.***
CAREER OBJECTIVE
Looking forward to work in a challenging and quality working environment, which has a scope for learning and professional development, thus enhancing my professional growth, and, thereby, adding value to the company.
PERSONAL TRAITS
•Ability to work as a team and independently.
•Good communicational skills.
•Punctual and dedicated towards work.
•Quick learner.
EDUCATION
GRIET HYDERABAD,TELANGANA
MTech(VLSI), Aug 2015
83.57%
VIDYA JYOTHI INST.OF TECHNOLOGY HYDERABAD,TELANGANA
BTech, Mar 2011
74.54%
KAMALA NEHRU POLYTECHNIC FOR WOMEN NAMPALLY,TELANGANA
Diploma,April 2008
76.3%
FRONTLINE SCHOOL HYDERABAD,TELANGANA
SSC,April 2005
88%
PROJECT DETAILS
PROJECT #1
NAME :MSIC TEST PATTERN GENERATION USING LFSRs
LANGUAGE USED :verilog
PROJECT DURATION :1 year
TOOLS :Cadence,Xilinx
PROJECT #2
NAME : MULTICHANNEL MISSING EVENT DETECTOR WITH
VOICE INDICATION.
LANGUAGE USED : Embedded C
NO.OF INDIVIDUALS : Three
PROJECT DURATION : Six Months
PROJECT#3
NAME : INTELLIGENT FIRE DETECTION FOR RAILWAYS
LANGUAGE USED : Embedded C
NO.OF INDIVIDUALS : Three
PROJECT DURATION : Three Months
PROJECT#4
NAME : SLEEP TIMER WITH ALARM
NO.OF INDIVIDUALS : Six
PROJECT DURATION : Six months
ACHIEVEMENTS:
•Presented a paper regarding ”AUDIO SPOTLIGHTING” at Institute of Aeronautical Engineering ” TESLA 2K10” A National Level Technical Symposium.
•Qualified in GATE 2013.
COMPUTER LITERACY
•Operating Systems: Windows 7/8,UNIX (UBUNTU)
•MS-Office.
TECHNICAL SKILLS:
•C,C++
•Core java
•VHDL,Verilog
•Cadence tools,Xilinx tools
•Quarters II
PERSONAL DETAILS
•Date of Birth : 23rd December 1989.
•Gender : Female.
•Father’s name : G. Sudershan.
•Permanent Address : House No:5-3-165, 3rd floor, Shanthinagar
Kukatpally, Hyderabad-500072.
•Languages Known : Hindi,English,Telugu.
DECLARATION
I hereby solemnly affirm that the particulars mentioned above are true to the best of knowledge.
Place :
Date :
(G.JYOTHI)