Email Id : email@example.com
To work in a learning environment where my skills will be enhanced and will provide foundation for a better career growth in my area of interest.
Examination Institution Board or university CGPA/Marks Year of passing
M. Tech in
Indian Institute Of
Deemed University 8.85/10
BPIT, Guru Gobind Singh
Guru Gobind Singh
12th N.C.J.P.S, Punjabibagh,
CBSE 84% 2008
10th S.T Thomas School,
CBSE 94% 2006
PROJECTS DETAILS TECHNOLOGY & SOFTWARES
MINOR & MAJOR PROJECTS
1) ROBOT ON WHEELS :
The project aims at making a 4- wheeled moving
system ( Robot ) that traverses its path according to the directions given to it through a wireless system 2) AUTOMATIC ROOM LIGHT CONTROLLER
WITH PASSWORD BASED DOOR LOCKING
SYSTEM USING 8051 :
The project aims at developing an embedded system
that has an automated room lights control and
provides a secured entry to the user
8051 Microcontroller, Assembly
( M.Tech )
FABRICATION OF MOS CAPACITOR :
The project aims at fabrication of MOS capacitor
having SiO2 as an oxide & analysation of it C-V
VLSI Fabrication technology
( M.Tech )
1) TRAFFIC LIGHT CONTROLLER: It controls the
ongoing traffic on a national and state highway.
2) VISITOR COUNTER: It counts the number of
persons entering or leaving a room.
3) REAL TIME DIGITAL CLOCK: Displays time on
a real basis.
SPARTAN 3-E FPGA,
Title : FPGA IMPLEMENTATION OF MEMORY FOOTPRINT REDUCED DELAY EFFICIENT 2D FIR FILTER: This involves physical implementation of Non- Separable structure of a 2-D FIR filter focussing primarily on the trade-off between area, delay & memory. Tools Used : Synopsys ( DC Compiler ), Xilinx, MATLAB Hardware Used : SPARTAN 3-E FPGA
Technology used: 180 nm
Have undergone training at BEL (Ghaziabad) for 6 weeks during 2 nd
years of graduation.
Projects Made: Project on “ STUDY OF ATE ( AUTOM ATIC TEST EQUI PMENT )”
(JUNE- JULY 2010)
Project on “STUDY OF IFF ( IDENTIFICATION OF FRIEND OR FOE ) RADAR”
(JUNE – JULY 2011)
WORKED AS A PRODUCT VALIDATION ENGINEER AT MENTOR GRAPHICS, NOIDA, INDIA PVT. LTD. ( July 2015 to Nov 2015 )
Worked on Timing tool & Flow Tools :
Optimus : Preparation & Validation of testcases.
Olympus & Nitro : Running PNR Flow on various designs to analyze QOR & timing impact by both the tools. WORKED AS A TEACHING ASSISTANT AT INDIAN INSTITUTE OF INFORMATION TECHNOLOGY (July 2013 to May 2015)
Allahabad, U.P., India
(A centre of excellence in Information Technology and allied areas) Worked as a Teaching assistant which involved demonstration of experiments & providing guidance to B.Tech students for courses like Microprocessor (8086), Digital Communication & Control Engineering in their respective labs.
HDL : Verilog, Assembly Language ( 8051), TCL, Basics of Perl, C,C++ & Core Java EDA Tool : Xilinx ISE 14.2, Optimus, Olympus, Nitro, Design Compiler Domain : FPGA, Embedded Systems, STA, Physical Design, Microprocessor, Microcontroller, Digital Designing, RTL Coding,, VLSI, Testing & Verification AREAS OF INTEREST
Front End VLSI Design
Testing & Verification
Secured a GATE score of 439 in 2013
Won the 2
prize in ‘EC Quiz’ held at IIITA in 2013
Acquired a certificate of participation in “IEEE Sponsored Student Leadership Workshop”
Participated in many inter school quiz competitions and cultural activities.
Worked as a volunteer in INSPIRE committee during SEVENTH SCIENCE CONCLAVE at IIIT-Allahabad