Md. Manzur Rahman
***** ****** ****, *** ****, Austin,Tx-78758
To obtain a full time senior engineering position. E DUCATION :
M.Sc- ECE,UT Austin. Integrated Circuit and System Track, Graduation date-May,2011, GPA-3.73/4
B.Sc.-Bangladesh University of Engineering and Technology(BUET) Graduation date-January,2008,GPA-3.96/4
INDUSTRY EXPERIENCE :
-Custom Circuit Design Engineer ar MediaTek, USA. 05/2014 to current.
-Design and verification of custom mixed signal blocks for leakage current sensor of ARM CPU.
-Design of current mirror, IDAC, Level shifters, Dynamic comparators, static comparators, Clock generator in 20SOC and 16Finfet process.
-Design and verification of 6-T SRAM based cache memory in 16FFP.
-Design and verification of 8-bit SAR ADC.
-Guide the layour engineer for circuit implementation.
-SRAM circuit designer at Oracle Inc. 06/2011 to 05/2014.
•Working on multi cycle Register file (8 Read, 4 write) design with TSMC 20nm Process to obtain High Target Frequency. Involved in custom design of decoder, D-Flop for time borrowing, custom gates for wordline, keeper and pre-charge drivers, sizing devices, custom Mux for area reduction and speed up option. Designed the array with 1R1W 8T cell which is used as 8 Read, 4 write register file externally.
•Working with layout engineers for floor planning, routing and overall layout of macro to achieve smaller area and higher speed of that macro. I guided the use of metal layer, metal track allocation and use of continuous diffusion for the custom driver devices to obtain higher speed.
• Worked with RTL team and Integration team to solve macro to macro architectural path timing issue.
• Working on power optimization of the register file. Used clock gating and data gating scheme for that. Changed decoding scheme and tried to share flops to reduce more power.
•Also, worked with RTL designer and neighbor block's owner to reduce more power.
• Used to read RTL in each release and generate LEF file and SynT Files for current macro and delivered to Integration team.
• Worked on margin analysis and fixing the issue of the macro.
•Worked on Prime time based tool to verify the timing of the block.
•Working on IR drop analysis and fixing the issue.
•Also, worked on 6T cell based macro for feasibility analysis. Tried different combination of flops, decoding strategy and architecture of SRAM(number of entry on a bitline, pulldown device, glitch latch etc.).
•Worked on the differential sensing scheme with sense-amp and single ended sensing scheme on 6T array.
•Worked with DFT team and defined the DFT scheme for the macro and designed DFT compatible input flops.
-MARVELL SEMICONDUCTOR INC. 02/1/2011-05/2011.
Worked in Global PNR group and did Static timing analysis,Place and routing. Lef and SynT File generation, use Prime time for timing analysis.
-Silicon Audio, Austin, TX -06/1/2010-08/25/2011
Used verilog and cadence to design read out circuit for MEMs device. RELATED GRAD COURSES
• VLSI1 • VLSI2 • VLSI Testing • Analog IC design • Mixed Signal IC design • Analysis and Design of VLSI Analog-Digital Interface Integrated Circuit •Digital signal Processing •Electro-mechanical Transducer RELATED UNDERGRAD COURSES
• VLSI Circuits • Digital Techniques • Signal and Systems • Digital Signal Processing
• Microprocessor and Digital Computer •Introduction to Digital communication
• Semiconductor Devices • Electromagnetic Fields & Waves • Biomedical Engineering RESEARCH EXPERIENCE:
SRAM Circuit: Design and verification of high speed 6T and 8T SRAM circuit by introducing scheme to allow write and read in the same cycle. The design was not phase based, but self timed,i.e read and write was completed in parallel.
SAR ADC: Proposed a new algorithm of Successive Approximation ADC and working on it including SRAM circuit for better performance on TSMC 180nm process. MEMS Seismometer- Involved in designing the read out circuit and control system of the project of Silicon Audio,Austin,TX.
Experienced in using • CADENCE Virtuoso • CCF and Encounter for place and routing •Primetime static Timing analyzer •MATLAB •HSPICE •VERILOG •Labview •Modeling of conventional MOSFET characteristics •Perl
COURSE RELATED LABS:
• Implement and optimize a 4-bit SRAM cell using 45nm CMOS
• Model and characterize a 32-bit X 32-bit memory array
•Designed of a Synchronous Serial Port (SSP) module using Verilog.
•Designing of a bus controller, consisting of a master and slave module, using Verilog hardware description language. Integration of the ARM core module with the designed modules and testing functional correctness .
•Design a 16bit High Speed Adder and 16bit ALU.
• 6T based SRAM design for simultaneous read and write to the same bitcell using self-times scheme.
•All Digital PLL design-Designed Current controlled oscillator .
•Modeling and Analysis of Burst noise effect on the performance of Δ-Ξ(Delta-sigma) Modulator.
•OPAMP design-Designed Op-amp with DC gain-110 dB, GBW-106Mhz, PM-600,CMRR-120dB
• OR1200 Microprocessor Design-Synthesized IFU Block.
•Design the BIST hardware-Designed with LFSR,MISR and scan chain using Verilog. UNDERGRADUATE PROJECTS:
•Senior year Thesis – Inversion Layer properties of <110> uniaxially strained Silicon n-channel MOSFET. PUBLICATIONS :
• Manzur et al,”Algorithm and Implementation of Digital Calibration of Fast Converging Radix-3 SAR ADC
” submitted in ISCAS 2014.
• Long Chen, Manzur Rahman and Nan Sun,”A Fast Radix-3 SAR Analog-to-Digital Converter ”-accepted in MWCAS 2013.
• Rahman, S.N.; Faraby, H.M.; Rahman, M.M, "A Theoretical Analysis Of Electrostatic Properties of <110> Uniaxially Strained Silicon n-Channel MOSFET”, Proceedings of Student Paper Contest, IEEE Electron Device Society Bangladesh Chapter, pp. 5-8, 2007.
• Rahman, M.M. et al "A Theoretical Approach for Familiarization with Techniques of Interleaved Echo-Planar Imaging for Functional Magnetic Resonance Imaging and Their Features”, International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE 2008),pp-143-148,2008
• Manzur et al "Microprocessor Based Design of the ControlMechanism of Automatic Mail Sorting Machine ", proceeding of International Conference on Computer Science and Software Engineering (CSSE), pp-1170- 1176,Volume-1,2008.
• Rahman, S.N.; Faraby, H.M.; Rahman, M.M.; Huda, M.Q.; Haque, A.; "Inversion Layer Properties of < 110 > Uniaxially Strained Silicon n-channel MOSFETs", International Conference on Electrical and Computer Engineering (ICECE),pp-438-441,2008.
AWARDS & HONORS :
•Hixon Fellowship award in UT Austin for Academic Excellence in 2010-2011.
• Student paper contest award, IEEE ED Bangladesh Chapter, 2007
•Dean’s list award and University Scholarship Merit list award in the Bangladesh University of Engineering and Technology 2004-2007.
VISA Status: Permanent Resident.