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Design Project

Location:
Bengaluru, Karnataka, India
Posted:
December 22, 2015

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Syed Moddasir Mokhtar Profile

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Syed Moddasir Mokhtar

Trainee in VLSI Design at IIVDT

Contact No # 91-961*******

Mail: acsvs3@r.postjobfree.com, acsvs3@r.postjobfree.com. Objective: Looking for Design and Verification Engineer position in an organization to apply best practices and utilize with skill set of Verilog, test benches & verification techniques, along with hands-on experience on Cadence based Full Custom Flow, back-end Cadence based Physical Design. Highlights:

Having Six Months Internship experience in VLSI Designing on CADANCE Based tool

Expertise in Custom Layout, DRC, LVS, ERC, RC Extraction & Post Layout Verification

Expertise in Synthesis, Static timing analysis, Floor Planning, Power Planning and Placement

Expertise in Clock tree synthesis, Routing

Expertise in Physical verification

Experience in HDL coding Verilog, Functional Verification in System Verilog

Knowledge of Bit cell characterization

Experience in various technologies - 65nm, 90nm, 180nm Education:

PG Diploma in VLSI Design & Training 2013 to 2014

Engineering Graduation

(Electronics and Communication, Integral

University)

B Tech

2009-2012

Diploma Engineering (Electronics and

Communication Engineering)

2005 to 2008

Training:

IIVDT Training on ASIC Design based on Cadence flow. Hands on experience with industry level projects, Design specification, HDL coding in Verilog, Simulation and Verification techniques working on ASIC design flow using CADENCE tool suite, plus Physical designing (back-end/layouts) on Virtuoso/CADENCE tool. Functional Skill Set:

Ability to work in a team of developers and co-ordinate smooth delivery of the project.

Strong Client facing skills.

Problem solving capability peered with strong communication skills. Syed Moddasir Mokhtar Profile

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Technical Skill Set:

RTL Coding Verilog

Functional Verification System Verilog

Custom Layout Design Cadence Virtuoso

Synthesis RTL Compiler

Physical Implementation SOC Encounter

Physical Verification Assura

Scripting Languages PERL,Shell and TCL

Operating Systems Windows 2000/XP/2003/Windows

7/Linux

Professional Experience:

Trainee at IIVDT (Aug 2013- APR 2014)

Strengths:

SDLC/Design Flow

End to end development

Innovative approach

VLSI Domain

Result Oriented

Strong English Communication

SUMMARY/SNAPSHOT

Experience in HDL coding Verilog, Functional Verification in System Verilog

Expertise in Custom Layout, DRC, LVS, ERC, RC Extraction & Post Layout Verification

Expertise in Synthesis, Static timing analysis, Floor Planning, Power Planning and Placement

Expertise in Clock tree synthesis, Routing

Expertise in Physical verification

Experience in various technologies - 65nm, 90nm, 180nm.

Interacting with the client to understand the project and finalize its scope.

Estimation, design and development of various modules.

Bug fixing and maintenance of the product

Syed Moddasir Mokhtar Profile

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Project Experience:

Projects – PG Diploma in VLSI Design

RTL Designing

Aug 2013 – Sep 2013

FIFO Design

Traffic Signal Controller

Sequential Multiplier Design

Digital Alarm Clock Design

Stop Watch Design

8-Bit Serial ALU Design

Tools: NC Verilog, HDL Coding in Verilog

Functional Verification

Sep 2013 – Nov 2013

Switch (Packet based protocol)

APB Protocol

Memory

Counter

Tools: NC Verilog, Verification on System Verilog

Physical Design & Verification of DTMF Chip

Dec 2013 – Feb 2013

Objective : To do the floor planning, Power planning, placement, CTS, Routing, Design signoff, Generating GDS II.

Tools : SOC Encounter, RTL Compiler

Gate count / Area : 6K

No. of Clocks : 2

Macro count : 4

Frequency : 125 MHz

Utilization : 70.1 %

Technology / Layers : TSMC 0.18 microns / 6 Metal Layers Role:

Floor Plan, Power Plan, Placement, Trial Route.

Timing Analysis, CTC, Detail Routing.

To observe the relation between core utilization, wire length and number of metal layers. Syed Moddasir Mokhtar Profile

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Physical Design & Verification of FIR Filter

Dec 2013 – Feb 2014

Objective : To do the floor planning, Power planning, placement, CTS, Routing, Design signoff, Generating GDSII.

Tools : SOC Encounter, RTL Compiler

Gate count / Area : 30K

No. of Clocks : 1

Macro count : 0

Frequency : 125 MHz

Utilization : 74.5 %

Technology / Layers : TSMC 0.18 microns / 6 Metal Layers Role:

Floor Plan, Power Plan, Placement, Trial Route.

Timing Analysis, CTS, Detail Routing.

To observe the relation between core utilization, wire length and number of metal layers Custom Layout & Verification

Objective : Schematic Design, Layout Design & Verification (DRC, LVS, ERC) of all the Gates, Oscillator, Static RAM, Differential Amplifier. Tools : Virtuoso Schematic Editor, Spectre, Virtuoso Layout Editor, Assura Technology / Layers : gpdk180 / 6 Metal Layers

Role:

Schematic Design on Virtuoso Schematic Editor.

Circuit Simulation on Spectre Tool.

Layout Design on Virtuoso Layout Editor.

Physical Verification, DRC, LVS, ERC on Assura.

Simulation with Parasitic Extraction on Spectre. Project – B.Tech (Electronics & Communication)

Wireless Battery Charger

Description- Wireless charging may one day replace plugs and wires similar to how Wi-Fi and Bluetooth have modernized personal communication. Wireless charging with inductive coupling uses an electromagnetic field that transfers energy from the transmitter to the receiver. Project- Diploma (Electronics & Communication)

Microcontroller based Braille

Description- It’s a data recognition for blind people. It provides better accuracy, less manual efforts and higher efficiency.

Syed Moddasir Mokhtar Profile

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Industrial Training

Mobile Communication and UMTS Networks

Description- Analyzing and study of mobile communication networks, 2G and 3G signal and data networks wireless technology

Passport Details:

Passport No –L5284530 Place of Issue: Patna

Date of Expiry: 11 Nov 2023

Personal Details:

Father’s Name Mr. Syed Mukhtar Ahsan

Date of Birth 22/ 12 / 1988

Gender Male

Marital Status Unmarried

Languages Known English, Hindi.

Passport Have valid passport

Declaration:

I hereby declare that all the information mentioned above is true and genuine to my knowledge and belief.

Place: Bangalore

[Syed Moddassir Mokhtar]



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