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Design Training

Location:
New Delhi, Delhi, India
Posted:
December 23, 2015

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Resume:

AJAY SINGH

V.P.O-Dugana,Teh-Paonta Sahib, Distt.-Sirmour

Himachal Pradesh, Pin Code-173029

Contact No.: +919*********

Email: acsv4c@r.postjobfree.com

Career Objective:

To work for an organization where I can maximize my skills and knowledge, a place that provides opportunities, and value individual ideas for mutual growth.

Educational Background

Qualification

School/University

Board

Year

Aggregate (%/CGPA)

B.Tech.

Bahra university

2011-2015

6.84(CGPA)

SENIOR SECONDARY

J.N.V. Nahan

C.B.S.E

2010

70%

MATRICULATION

J.N.V. Nahan

C.B.S.E

2008

77%

INDUSTRIAL TRAINING:

Company : DKOP Labs Pvt. Ltd.

Title : VLSI Design

Duration : Five Month (from Jan to May 2015)

TECHNICAL SKILLS:

LAGUAGES :- Verilog

OPERATING SYSTEM:- WINDOWS 7/8

SIMULATION TOOL:- Modelsim, Xilinx

DESIGNING TOOL KIT :- FPGA

STRENGTHS:

Disciplined, Adaptability, Dedication, Hard working.

PROJECTS:

Design of five port parallel router for network-on-chip using Verilog HDL.

Objective: - to understand the practical usage of router for NoC by which communication network can be made for designing Multiprocessor system- on- chip (SoC).

Arithmetic processor for ALU(arithmetic & logical unit) using Verilog HDL

Objective: - To study the practical implementation of Verilog language for VLSI.

Personal Profile

Name

Ajay Singh

Sex:

Male

Date of Birth:

15th july,1992

Linguistic Proficiency:

English, Hindi

Phone:

+919*********

E-mail:

acsv4c@r.postjobfree.com

Married Status

Single

Hobbies

Trekking, photography, cooking, listening music

DECLARATION

I hereby declare that information furnished by me is true to the best of my knowledge and belief.

AJAY SINGH

DATE: 14 October 2015

PLACE: gurgaon



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