V.P.O-Dugana,Teh-Paonta Sahib, Distt.-Sirmour
Himachal Pradesh, Pin Code-173029
Contact No.: +919*********
To work for an organization where I can maximize my skills and knowledge, a place that provides opportunities, and value individual ideas for mutual growth.
Company : DKOP Labs Pvt. Ltd.
Title : VLSI Design
Duration : Five Month (from Jan to May 2015)
LAGUAGES :- Verilog
OPERATING SYSTEM:- WINDOWS 7/8
SIMULATION TOOL:- Modelsim, Xilinx
DESIGNING TOOL KIT :- FPGA
Disciplined, Adaptability, Dedication, Hard working.
Design of five port parallel router for network-on-chip using Verilog HDL.
Objective: - to understand the practical usage of router for NoC by which communication network can be made for designing Multiprocessor system- on- chip (SoC).
Arithmetic processor for ALU(arithmetic & logical unit) using Verilog HDL
Objective: - To study the practical implementation of Verilog language for VLSI.
Date of Birth:
Trekking, photography, cooking, listening music
I hereby declare that information furnished by me is true to the best of my knowledge and belief.
DATE: 14 October 2015