Design System

RESUME

POONAM KUMARI

E-mail Id:- ************.******@*****.***

Mobile: +91-895*******

Career Objective :

To establish a successful career in the field of VLSI in a leading semi-conductor industry that enables personal and professional growth and be sincere in the profession I take up.

TECHNICAL SKILLS:

Good Knowledge in Both BACKEND AND FRONTEND VLSI

Good knowledge of DIGITAL LOGIC DESIGN CONCEPTS

Good in writing RTL models in VERILOG

Good knowledge in SYSTEM VERILOG

Good knowledge in UVM Verification

Basic knowledge in ANALOG CIRCUIT

Good knowledge of PHYSICAL DESIGN FULL FLOW

FLOOR PLANING, PLACE & ROUTE, CLOCK TREE SYNTHESIS,

POWER PLANNING, IR DROP, ELETROMIGRATION,CONGESTION

Good knowledge of STATIC TIMING ANALYSIS

Basic knowledge of CMOS CIRCUIT

EDA Tools:

Xilinx :- Xilinx ISE

Mentor Graphic Tools :- Questa Sim/ModelSim

Logic Synthesis :- Cadence Encounter RTL Compiler

Physical Design :- Cadence Soc Encounter

Experience:

Currently working as ASIC Design and Verification Intern in Maven Silicon SofTech Pvt ltd, Bangalore.

** GATE 2014 Qualified And Gate Score -346

Professional Qualification:

Maven silicon Certified Advanced VLSI Design and Verification Course

from Maven Silicon VLSI Design and Training Center, Bangalore

Physical Asic Design Course From Indian Institute Of VLSI Design And Training

Academic Record:

Qualification

Institution

Year of Passing

Percentage

Advanced VLSI Design and Verification Course

Physica Design Course

Maven Silicon Center

IIVDT bangaore

2014

2015

70.00%

B. Tech

Electronics and Telecommunication

2012

73.50%

CGPA:7.85

HSLC

Nalanda Open University

Patna, Bihar

2008

60.55%

SSLC

Jawahar Navodaya

Vidyalaya, Gaya

2005

80.00%

INTERNSHIP EXPERIENCE:

PROJECT : Dual Tone Multi-Frequency (DTMF) receiver

Language TCL Language

Tools Cadence Soc Encounter

Technology 90nm, 6metal layer

Summary To done Floor Planning, Placement,power planning Clock Tree Synthesis, Routing

Cell Count: 10k

Macro Count: 20

Responsibilities Learnt Floorplan, power planning, PnR, Clock Tree Synthesis.

PROJECT: AHB2APB BRIDGE– RTL Design & Verification

RTL Design : Verilog HDL

Tb Methodology :UVM

EDA Tools: Modelsim, Xlinix ISE

The AHB to APB bridge comprises a AHB slave, APB master, which is used to control Generation Of the APB and AHB output signals, and the address decoding logic which is used to Generate the APB peripheral select lines.

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

VLSI PROJECT:

Working On SPI CORE(Serial Peripheral Interface ) – Verification

HVL: System Verilog Tb Methodology :UVM

EDA Tools: Modelsim

SPI (Serial Peripheral Interface) is serial, synchronous, full duplex communication protocol. It is widely used as a board-level interface between different devices such as microcontrollers, DACs, ADCs and others.

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

ROUTER 1X3 DESIGN AND VERIFICATION

HDL: Verilog

HVL: System verilog

Methodology: UVM

EDA Tools: Model sim, Questa – Verification Platform and ISE

Router is a packet based protocol Router drives the incoming packet which comes from

The input port to output ports based on the address contained in the packet.

Architected the design

Implemented the RTL using Verilog HDL

Verified the RTL using Verilog

EXTRA CURRICULUM ACTIVITIES:

Seminar on “Global positioning System” in 7th semester and Gained hieghet Marks

I have participated in “Painting Exhibition” held in our college and Won first prize

I have participated in “Hindi Quotes” held in our school and Won 2nd prize

Department first in 5th and 6th semester of engineering

GATE QUALIFIED in 2014 and gate score is 346

Strenghts:

Interested in rapid change in technology

Basic knowledge of technical subjects

Good decision making and quick problem solving skill

Personal profile:

Father Name : Anil kumar

Date of Birth : 26-02-1990

Gender : Female

Nationality : Indian

Present Address : Arekere micolayout

7th cross,omkar nagar Bannarghatta Road

Permanent Address : nawabganj Road Makhdumpur

Jehanabad BIHAR

Language known : English, Hindi

Hobbies : singing, Reading biography of great person

DECLARATION:

I hereby declare that the above mentioned information is correct and I bear the responsibility for the correctness of the above mentioned particulars.

Place: Bangalore [Poonam kumari]

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