High School Project

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. SRIKUMAR CHENDOLA

Phone: +91-988******* Email:***********@*****.*** Bangalore, India

OBJECTIVE

To be part of an organization that offers me wide scope and opportunity to enhance my credentials, so that I can contribute my best towards the growth of the organization. EDUCATIONAL QUALIFICATION

M.Tech in VLSI Design from Manipal University in 2015.(8.51 CGPA)

B.Tech in Electrical & Electronics from P.B.R Viswodaya Institute of Technology and Science, affiliated to JNTU in 2011.(69)

10+2 from Sri Chaitanya Junior college,Nellore affiliated to Board of Intermediate Education, Andhra Pradesh in 2007.(86.67)

SSC from Sri Netaji(M.S.R) Pilot High School, Nellore affiliated to Board of Secondary Education, Andhra Pradesh in 2005.(65)

INDUSTRIAL EXPERIENCE

Intern at GRID INDIA, BANGALORE from 01-07-2014 to 04-04-2015 Project 1 : Designed USB 3.0 SUPER SPEED PHYSICAL LAYER. Tool used : Xilinx ISE Design suite.

Language : Verilog HDL

Description : A PHY is a transmitter and receiver that operate together and are located on the same component. A channel connects two PHYs together with two unidirectional differential pairs of pins for a total of four wires.

Developed scrambler in Transmitter side.

Developed 8b/10b Encoder in Transmitter side.

Developed 10b/8b Decoder in Receiver side.

Project 2 : Verified USB 3.0 SUPER SPEED PHY LAYER Tool used : Questa Sim 10.0b

Language : System Verilog

Description : Developed test bench components using System Verilog. TECHNICAL SKILLS

Programming languages : C, OOPS.

Scripting language : Perl,

Synthesis Tool : RTL Complier

EDA Tools : Cadence Virtuoso, Cadence NC Launch, Questa Sim 10.0b.

HDL Language : Verilog HDL.

HVL : System Verilog

2

ACADEMIC PROJECTS

Redefining CMOS Logic Style for Sub threshold Operation In this work, a new CMOS logic style, that results in reduced leakage currents both in active and idle modes of operation leading to a better Static and dynamic performance is proposed. Logic styles, such as Transmission gates, NAND, 1-bit Full adder digital circuits. For these circuits we developed a layouts and checked the DRC.

Duration : 5 Months

Technologies : 180nm and 90nm Using Cadence virtuoso

Implementation of OPEN NAND FLASH INTERFACE using Single Data Rate Role : Designed “ONFI 3.2”, using Verilog HDL

Duration : 5 Months

Simulation Tool : Cadence NC Launch

Synthesis Tool : Cadence RTL compiler

Responsibilities :

Developed design using Verilog

Mitigation of VOLTAGE SAGS/SWELLS using DVR

This work describes the techniques of correcting the supply voltage sags and swells in a distribution system by DVR (dynamic voltage restorer).A new pwm-based control scheme has been implemented

Duration : 5 Months

Technology : Pulse width modulation (PWM)

ACHIEVEMENTS

I got ALL INDIA Rank in Manipal University Entrance Exam 2013.

Performed several stage shows in school and college.

Actively participated in college festivals and departmental fair. DECLARATION

I hereby declare that above mentioned information is true to the best of my knowledge. Place: Bangalore SRIKUMAR CH

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