KARTHIKEYA A

Systems Engineer at RAMBUS CHIP TECHNOLOGIES

990-***-****/849-***-****

acr85q@r.postjobfree.com

Objective To secure a challenging position where I can effectively contribute my skills as a professional, possessing competent skills.

Skills Technical

Languages: Verilog, Perl and Basics of TCL, SQL/PLSQL

Tools:

Cadence Virtuoso 64

Xilinx

Altera Modelsim

Informatica 9.1.

SQL Server 2008.

Toad

Lab-station

Trainings

Informatica

SQL server 2008

MSBI

UNIX, Perl Scripting.

SQL/PLSQL

………

Core Competencies

Well versed with digital design concepts and basic applications of analog.

Good knowledge of ASIC design flow and SOC

Good knowledge of Verilog and Perl Scripting Basics.

Result oriented with strong analytical, problem solving, and communication skills.

Good knowledge on Informatica Transformations and SQL Server stored procedures.

Good knowledge on SQL and PLSQL.

Have ability to effectively interact and coordinate with the team to meet the project related deliverables.

Worked on on DDR3 (Double Data Rate) DRAMs and working on Low power version of DDR3 (LPDDR3).

………

Experience Rambus Chip Technologies

Oct 2014 –Present Intern

Working on DDR3 (Double Data Rate) DRAMs and working on Low power version of DDR3 (LPDDR3).

Working on setting up of platform between Physical channel and DRAM for mobile applications.

Performing characterization like calculating Driving Impedance, Power, Settling time and Holding Time, Preamble Postamble etc.

Working on Lab station tool and running the Perl scripts to perform Characterization Tasks.

S

Cognizant Technology Solutions

Feb 2011 – July2013 Programmer Analyst

Worked on development projects that included Teradata, Unix, SQL Server 2008, Oracle SQL Developer and Informatica

Involved in various phases of SDLC

Involved in the preparation of Technical Design Documents in all the projects.

Developed BTEQ Scripts, Mappings and Workflows as per the given requirements and tested the same in all environments.

Worked in creating the Work orders, incidents and sending migration requests during migration of code.

Involved in coding SQL and testing the Database according to the requirement.

Project & Research “BRING UP OF A MEMORY SUBSYSTEM FOR MOBILE PLATFORMS” as research at Rambus Chip Technologies.

Oct 2014 – June 2015

To demonstrate how to set a platform to communicate with a LPDDR3 device.

For this communication we need a compatible controller and a physical layer.

The typical steps involved to configure a CPHY (Controller PHY) are to issue signals for LPDDR3 device.

CPHY includes power on initialization flow (Reset sequence and internal calibrations).

Initialize the Memory by issuing proper command sequence from CPHY.

A sequence of handshake establishes a connection between controller and memory.

Once the connection is established the channel is ready for Writing and Reading from Memory.

“Self-Testing and Self Repairing Adder using Fault localization [Presented in SET Conference at VIT University]

May2014 – Oct 2014

Implementation of Full Adder, Carry Save Adder and Ripple Carry Adder in Cadence Virtuoso 180nm Technology.

Measured Power, Area and Timing of different adder blocks along with the Bandwidth Measurement.

Coded using Verilog language in NC Launch of Cadence tool

“A Low Power 1.2 GS/s 4-Bit Flash A/D Converter in 180nm CMOS”[Presented in NCSET Conference organized by VIT University] Nov 2013 – May 2014

Designed 1-bit, 2-bit, 4-bit and 16-bit Comparator in cadence virtuoso tool and compared Area, Power of each comparator.

Coded in Verilog for low power and reusability of blocks.

Achieved Low Power and High Bandwidth and this improve the Performance.

“FPGA implementation of MFCC Feature extraction for low cost speech recognition systems”

Jun2013 -Nov2013

The existing algorithm is implemented using Verilog in XILINX.

MFCC front- end design that is advantageous in both cost and performance also by maintaining the simple pipelined structure.

“Design of 8-bit DLX RISC Processor”

Jan2014 – May 2014

Design of various modules of processor such as ALU, register file, program counter, instruction decoder, stack, multiplexer and status register.

Data path and Controller are designed by integrating these modules.

ASIC design flow is followed to obtain the area, power and timing report.

Tools-Xilinx, Cadence® Encounter, RC,NC launch.

“Traffic Signal Controller for Emergency Services

Using RF” at BMSIT Bangalore

Jan – June 2010(B.E)

This is a concept where we are designing an automated controlling of traffic signals by some emergency service vehicles like Ambulance, Fire Engine and VIP vehicles etc.

Here the driver will be having access to control the traffic lights just by pressing the buttons provided.

Depending on the place of presence of his vehicle the signal will be kept open for some time and resets automatically.

Work Experience and Project Details

At Cognizant Technology Solutions Bangalore

Have 2.5 Years of work experience in IT Industry(Cognizant Technology Solutions) with experience in Data warehousing applications, Worked on development projects that included Teradata, Unix, SQL Server 2008, Oracle SQL Developer and Informatica.

Worked on projects like WLP-Provider Finder, ACS DW Phase2,WLP ESCS (WellPoint CorpApps LO), WLP - CC2(Comprehensive Care Phase 2), JS proteus reporting build.

Developed BTEQ Scripts, Mappings and Workflows as per the given requirements and tested the same in all environments, Worked on running Jobs through WLM and handled issues in the project

Worked in creating the Work orders, incidents and sending migration requests during migration of code.

Education

M.TECH in VLSI Design (2013 -2015) from VIT University with CGPA of 8.22.

Bachelor of Engineering in Telecommunication (2010) from BMSIT Bangalore with 80% Aggregate.

Pre University in PCMB (2006) from MES PU College, Malleshwaram, Bangalore with 87%.

10th from JBS High School, Pavagada, Tumkur District (2004) with 86%.

Activities

Member of IEEE Solid State Electronics Society, VIT University.

Listening to Music, Photography.

Playing Shuttle, Carom, Cricket and Playing chess.

Awarded Certificate on Informatica power Centre 8.0 and Teradata.

Personal Details

Date Of Birth : 14.11.1988

Father : P.V Ananth Ram Bhatt

Address : No.39, 9th Main R.K Layout,2nd Stage Padmanabhanagar Bangalore-560070

Languages known : English, Telugu, Kannada

Declaration: I hereby declare that all the information furnished above is correct to the best of my knowledge and belief

Place: Bangalore (Karthikeya A)

Contact this candidate