Merin E Johny Phone: 408-***-**** San Diego, CA Email: acqgse@r.postjobfree.com

SUMMARY OF QUALIFICATIONS

Technical Professional completed MS in Electrical Engineering @ SDSU, looking for Full time opportunities in Hardware Design, Test and Product engineering roles.

Course work and projects in VLSI Designing and Testing, Digital Signal Processing and ASIC design

Projects implemented in VLSI/FPGA using Verilog HDL

Skilled in Analog, Digital Simulation, Schematic and Layout using IC station Mentor Graphics, Cadence virtuoso.

ADC, DAC, ALU design, layout and test were optimized.

Two years work experience with extensive use of Java, SQL, Javascript.

Work Experience using C++ and MATLAB.

Comfortable using Oscilloscopes, probes, signal generator and other lab equipment.

Education

Masters in Electrical Engineering (Sept 13-Dec 15)

Specialization: VLSI circuit design, System design and ASIC Design.

San Diego State University, CA, USA GPA: 3.9/4.0

Bachelor of Science in Electrical and Electronics Engineering (Oct 06-June 10)

University Of Calicut, India GPA: 3.8/4.0

Related Coursework

VLSI Circuit Design, ASIC design, Signal and Power Integrity, Digital signal Processing, MEMS design and application, Microwave devices and Systems.

Technical Skills

Development Environment

MS DOS, Windows, Linux, Mac OS X,UNIX

Languages

Hardware

Software

C++,C, Verilog

Java, Perl

Simulation Tools

Cadence Virtuoso Spectre, Cadence,Mentor Graphics DRC check, PSpice, MATLAB Multisim, ICStation

Microsoft Office

MS Word, MS Excel, MS Outlook, MS Power-point

Laboratory Equipments

Oscilloscope, Digital Multi meter, Signal Generator and Soldering skills.

Projects

Digital design and testing (Jan15 – May 15)

Designed and tested an efficient DSP system, IIR and FIR filter in Verilog HDL and tested using verilog Test Bench

Time multiplexed architecture of Fixed point FIR and IIR cascaded filter was designed and implemented in verilog HDL and test bench using verilog was used to test the system.

FPGA implementation of highly efficient System was designed for doing Matrix Inversion For High Performance Embedded MIMO receivers-Implemented using Matlab and verilog - Improved the performance using Retiming, Pipelining.

Designing an efficient way of Matrix Inversion, verified using Matlab and Verilog HDL.

Applied various retiming and pipelining techniques to improve the performance.

Wrote test scripts to test the functionality of the System.

VLSI ASIC design: 20 bit pipelined Wallace tree multiplier tested using mixed signal simulation using NC Verilog Test-bench (Oct14-Dec14)

20 bit pipelined enhanced Wallace tree booth multiplier was implemented in cadence using various circuit families such as CMOS, Complementary Pass transistor, Transmission gates, domino logic

Ultra fast, 3.2ns low power 32 bit pipelined Adder using dynamic logic was implemented and tested using mixed signal simulation using NCVerilog Test-bench

Ultra fast low power 32 bit enhanced adder using multiple output domino logic, a re-configurable adder in implemented in cadence.

Power Integrity: Designed and optimized a board-level PDN (Oct14–Dec14)

Optimized PDN using PDN Expert tool from Giga Hertz Technology Inc.

Plane resonances at giga hertz frequency was investigated and appropriate decoupling capacitors were selected for optimization based on target impedance approach.

Signal integrity: 90ohm impedance differential line design and simulated the design and tested using Agilent ADS tool (Oct14-Dec14)

Rogers impedance analyzer tool was used to design the 90ohm differential line

Maxwell2D tool was used to verify the design and obtain per unit length inductance and capacitance matrices.

Agilent ADS tool was used to simulate the design and generate eye diagrams and analyze signal integrity and also plotted mixed mode S parameters.

VLSI circuit design: Flash Analog to Digital Converter and a subsystem of clocking using VCO based ring oscillator achieving a SNR of 27dB and Resolution of 5.03 bits (Oct13-Dec13)

A 6-Bit Flash ADC was designed using CMOS and optimized using Mentor Graphics, IC Station

Designed following subsystems of clocking a VCO based ring oscillator, sampling, comparator, encoder and register array

DRC check was performed on layout generated using LVS.

A-D converter showed correct functionality with high number of bits of resolution.

Digital Signal Processing: DTMF signal detector was designed and implemented using Matlab (Jan14–May14)

Designed an IIR filter to separate the low band and high band frequencies

Used Matlab for design and simulation.

Work Experience

Indian Space Research Organization, India (Dec 09–May 10)

Electrical Engineering Intern

Built an efficient algorithm (Walsh Hadamard Transform) to compute correlation method for system identification.

Worked in a team of senior research scientist for optimizing this algorithm to be used in aerospace power systems.

Extensively used MATLAB programming and C++ coding.

Tata Consultancy Services, India (Nov 10- Apr 12)

Systems Engineer

Worked as developer in Java platform for CITI online banking application in one of world’s biggest IT services provider.

Worked in a cross cultural team with both onsite and offshore worldwide teams.

Tools used: Eclipse JDK, SQL developer.

Achievements and Awards

Awarded 'Best Trainee', at Tata Consultancy Services, India

Coordinator at Technical Exhibition “RESONANCE' at Government Engineering College, India

Conducted various co-curricular activities in College.

Class Representative in Government Engineering College

Available for relocation

Work authorization available

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